S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 15

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
1.2.4. Vertical Timing
The vertical timing signals include VS, VAV, ODD, SCH, and PID.The VS is used for identifying the first line of video
in the vertical position. The VS leading edge can be programmed to either track the incoming video’s serration
pulses or to be aligned to the beginning of the video line or half way, as shown in Figure 36 and Figure 37. If
VALIGN = 0, the VS leading edge is based on the output of an internal low pass filter, and its location is dependent
on the noise conditions of the video input. The trailing edge of VS is locked to either the beginning of the video line
or half way. The half way location relative to the beginning of the video line changes depending on current input
standard and output format. If VALIGN = 1, the leading edge of the VS is aligned to the beginning of the video line
or half way. The trailing edge is always aligned to the beginning of the video line. The VSE bit in the CMDA register
can be programmed to shorten the VS falling edge by one horizontal line.The VAV signal is used for vertical
cropping. The start and stop lines for VAV are programmable through the VAVB and VAVE registers,
respectively.The ODD signal signifies the current field number. When ODD is active, the current field is 1 or 3 (or 5
or 7 if in PAL mode). The leading and trailing edges of ODD can be aligned to either the leading edge of VS
(VALIGN = 1) or the trailing edge of VS (VALIGN = 0). The signal may be used in conjunction with SCH and PID to
exactly identify the current field. To distinguish between fields 1, 2 verse fields 3, 4 (or fields 1, 2, 3, 4 verse fields 5,
6, 7, 8 for PAL) the phase of the color burst relative to the sync tip must be measured. That information is provided
by the PORTB(SCH) pin. The S5D2650 provides the output of a comparator that measures whether the current
color burst phase relative to the falling edge of the sync is greater or less than a predetermined constant. This
constant is controlled with SCHCMP[3:0]. The polarity of the SCH output pin depends on the current
Analog video input
Digital video output
SLICE
FS_PULSE
SYG
BPG
CBG
CBGW
FH2
HAV
HS1,2
ELECTRONICS
Figure 6.
Active video
Chip delay
Approximate Locations for the Horizontal Timing Signals
Blank
Active video
MULTIMEDIA VIDEO
PAGE 15 OF 95
7/18/03