S5D2650 Samsung Semiconductor, Inc., S5D2650 Datasheet - Page 55

• Manufacturer Part Number: S5D2650
• Description: Multistandard Video Decoder/scaler
• Manufacturer: Samsung Semiconductor, Inc.

S5D2650 Data Sheet
HAVB[10:0]
HAVE[10:0]
Index
Index
Index
HS1B[8:1] -
HS1BE0
0Ch
0Ch
0Ch
05h
06h
07h
Mnemonic
Mnemonic
Mnemonic
HXTRA
HXTRA
HXTRA
HAVB
HAVE
HS1B
ELECTRONICS
This 11-bit register is used to define the start location of the HAV signal relative to the sync tip
(for CVBS input, this is the composite video sync tip. For 8-bit CbYCr input, this is the leading
edge of the HS1 or EAV). The content of this register is a 2’s complement number which is
used as an offset to the default. The resolution for this register is 1 CK clock.
This 11-bit register is used to define the end location of the HAV signal relative to the sync tip.
The content of this register is a 2’s complement number which is used as an offset to the
default The resolution for this register is 1 CK clock.
If HS1 is programmed as an output, this 9-bit register defines the start location of the HS1
signal. The content of this register is a 2’s complement number which is used as an offset to the
default. The resolution for this register is 1 CK clock.
bit 7
bit 7
bit 7
HAVB[10:8]
HAVB[10:8]
HAVB[10:8]
bit 6
bit 6
bit 6
HAV Start Control
HS1 Start Control
HAV End Control
bit 5
bit 5
bit 5
bit 4
bit 4
bit 4
HAVB[7:0]
HAVE[7:0]
HS1B[8:1]
HAVE[10:8]
HAVE[10:8]
HAVE[10:8]
bit 3
bit 3
bit 3
bit 2
bit 2
bit 2
MULTIMEDIA VIDEO
HS1BE0 HS2BE0
HS1BE0 HS2BE0
HS1BE0 HS2BE0
bit 1
bit 1
bit 1
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bit 0
bit 0
bit 0
7/18/03