S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 51
S1D13505
Manufacturer Part Number
S1D13505
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13505.pdf
(566 pages)
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Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/02/02
Symbol
t11
t10
t12
t13
t14
t15
t16
t9
t1
t2
t3
t4
t5
t6
t7
t8
2
1
Clock period
Clock pulse width high
Clock pulse width low
A[20:0], M/R#, RD/WR# setup to CKIO
A[20:0], M/R#, RD/WR# hold from CS#
BS# setup
BS# hold
CSn# setup
Falling edge RD# to D[15:0] driven
Rising edge CSn# to WAIT# tri-state
Falling edge CSn# to WAIT# driven
CKIO to WAIT# delay
D[15:0] setup to 2
D[15:0] hold (write cycle)
D[15:0] valid to WAIT# rising edge (read cycle)
Rising edge RD# to D[15:0] tri-state (read cycle)
1.
2.
If the S1D13505 host interface is disabled, the timing for WAIT# driven is relative to the fall-
ing edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
nd
CKIO after BS# (write cycle)
a
b
Two Software WAIT States Required
One Software WAIT State Required
Parameter
Table 7-2: SH-3 Timing
15.1
Min
10
6
6
3
0
4
1
4
0
5
0
4
0
0
5
3.0V
a
Max
25
15
20
25
15.1
Min
2.5
3.6
2.5
10
6
6
3
0
4
1
4
0
0
0
0
5.0V
b
Max
10
10
12
10
X23A-A-001-14
S1D13505
Units
Page 45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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