MT54V512H18E Micron Semiconductor Products, Inc., MT54V512H18E Datasheet - Page 17

• Manufacturer Part Number: MT54V512H18E
• Description: 9Mb QDR SRAM, 2.5V Vdd, HSTL , 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Overview (continued)
address, data, or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction regis-
ter and through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.
EXTEST
to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in the
TAP controller, hence this device is not IEEE 1149.1
compliant.
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAM-
PLE/PRELOAD instruction has been loaded. EXTEST
does not place the SRAM outputs in a High-Z state.
IDCODE
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO pins/balls and allows the IDCODE to be
shifted out of the device when the TAP controller
enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset
state.
SAMPLE Z
scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.
SAMPLE/PRELOAD
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
512K x 18, 2.5V V
MT54V512H18E_16_A.fm - Rev 10/02
Instructions are loaded into the TAP controller dur-
EXTEST is a mandatory 1149.1 instruction which is
The TAP controller does recognize an all-0 instruc-
The IDCODE instruction causes a vendor-specific,
The SAMPLE Z instruction causes the boundary
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
DD
, HSTL, QDRb4 SRAM
0.16µm Process
17
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bi-directional balls is captured in the boundary
scan register.
clock can only operate at a frequency up to 10 MHz,
while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in
the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not
harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not
be possible.
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP con-
troller’s capture setup plus hold time (tCS plus tCH).
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in
the boundary scan register.
the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.
is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruc-
tion will have the same effect as the Pause-DR com-
mand.
BYPASS
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and
TDO. The advantage of the BYPASS instruction is that
it shortens the boundary scan path when multiple
devices are connected together on a board.
RESERVED
reserved for future use. Do not use these instructions.
When the SAMPLE/PRELOAD instruction is loaded
The user must be aware that the TAP controller
To guarantee that the boundary scan register will
Once the data is captured, it is possible to shift out
Note that since the PRELOAD part of the command
When the BYPASS instruction is loaded in the
These instructions are not implemented but are
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
, HSTL, QDRb4 SRAM
512K x 18
©2002, Micron Technology Inc.
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