isp1582 NXP Semiconductors, isp1582 Datasheet - Page 43

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isp1582

Manufacturer Part Number
isp1582
Description
Hi-speed Universal Serial Bus Peripheral Controller
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
Table 55.
ISP1582_6
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Interrupt Enable register: bit allocation
8.4.6 DMA Interrupt Enable register (address: 54h)
8.4.7 DMA Endpoint register (address: 58h)
TEST4
R/W
15
R
7
0
0
-
-
Table 53.
Table 54.
This 2-byte register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register. The bit allocation is given in
given in
Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is
disabled, with the values turning to logic 0.
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in
Bit
11
10
9
8
7 to 0
INT_EOT
1
1
0
R/W
14
6
0
0
-
-
-
Table
Symbol
EXT_EOT
INT_EOT
-
DMA_XFER_OK DMA Transfer OK: Logic 1 indicates that the DMA transfer is
-
reserved
DMA Interrupt Reason register: bit description
Internal EOT-functional relation with bit DMA_XFER_OK
DMA_XFER_OK
0
1
1
53.
R/W
13
5
0
0
-
-
-
Rev. 06 — 20 September 2007
Description
External EOT: Logic 1 indicates that an external EOT is detected.
Internal EOT: Logic 1 indicates that an internal EOT is detected; see
Table
reserved
completed (DMA Transfer Counter has become zero).
reserved
IE_GDMA_
Description
During the DMA transfer, there is a premature termination with
short packet.
DMA transfer is completed with short packet and the DMA
transfer counter has reached 0.
DMA transfer is completed without any short packet and the DMA
transfer counter has reached 0.
STOP
R/W
R/W
12
54.
0
0
4
0
0
reserved
Table
IE_EXT_
EOT
R/W
R/W
56.
11
0
0
3
0
0
Hi-Speed USB Peripheral Controller
IE_INT_
Table
EOT
R/W
R/W
…continued
10
0
0
2
0
0
55. The bit description is
reserved
R/W
R/W
9
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1582
XFER_OK
IE_DMA_
R/W
R/W
8
0
0
0
0
0
43 of 69

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