saf1761 NXP Semiconductors, saf1761 Datasheet - Page 38
saf1761
Manufacturer Part Number
saf1761
Description
Hi-speed Universal Serial Bus On-the-go Controller
Manufacturer
NXP Semiconductors
Datasheet
1.SAF1761.pdf
(166 pages)
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Table 21.
[1]
Table 22.
[1]
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 1
0
The reserved bits should always be written with the reset value.
For details on register bit description, refer to
Symbol
-
CF
CONFIGFLAG - Configure Flag register (address 0060h) bit allocation
CONFIGFLAG - Configure Flag register (address 0060h) bit description
8.2.5 CONFIGFLAG register
8.2.6 PORTSC1 register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in
The Port Status and Control (PORTSC) register (bit allocation:
well. It is reset by hardware only when the auxiliary power is initially applied or in response
to a host controller reset. The initial conditions of a port are:
If the port has power control, software cannot change the state of the port until it sets port
power bits. Software must not attempt to change the state of the port until the power is
stable on the port (maximum delay is 20 ms from the transition).
•
•
Description
reserved
Configure Flag: The host software sets this bit as the last action when it is configuring the
host controller. This bit controls the default port-routing control logic.
No peripheral connected
Port disabled
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
[1]
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial Bus Rev.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 18 November 2009
reserved
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
[1]
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
Table
R/W
R/W
R/W
R/W
23) is in the power
25
17
0
0
9
0
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
Table
R/W
R/W
R/W
R/W
21.
CF
38 of 166
24
16
0
0
8
0
0
0
1.0”.
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