saf1761 NXP Semiconductors, saf1761 Datasheet - Page 45
saf1761
Manufacturer Part Number
saf1761
Description
Hi-speed Universal Serial Bus On-the-go Controller
Manufacturer
NXP Semiconductors
Datasheet
1.SAF1761.pdf
(166 pages)
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Table 37.
Table 38.
[1]
Table 39.
SAF1761_1
Product data sheet
Bit
31 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 2
1
0
The reserved bits should always be written with the reset value.
Symbol
-
RESET_HC
RESET_ALL
HcScratch - Host Controller Scratch register (address 0308h) bit description
SW Reset - Software Reset register (address 030Ch) bit allocation
SW Reset - Software Reset register (address 030Ch) bit description
Symbol
SCRATCH[31:0]
8.3.3 HcScratch register
8.3.4 SW Reset register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
This register is for testing and debugging purposes only. The value read back must be the
same as the value that was written. The bit description of this register is given in
Table 38
Description
reserved; write logic 0
Reset Host Controller: Reset only the host controller-specific registers (only registers with
address below 300h).
0 — No reset
1 — Enable reset
Reset All: Reset all the host controller and CPU interface registers.
0 — No reset
1 — Enable reset
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Access
R/W
shows the bit allocation of the register.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 18 November 2009
Value
0000 0000h
reserved
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
Description
Scratch: For testing and debugging purposes
[1]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
RESET_
R/W
R/W
R/W
R/W
HC
25
17
0
0
9
0
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
RESET_
Table
R/W
R/W
R/W
R/W
ALL
45 of 166
24
16
0
0
8
0
0
0
37.
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