psd813f2v STMicroelectronics, psd813f2v Datasheet - Page 54

• Manufacturer Part Number: psd813f2v
• Description: Flash In-system Programmable Isp Peripherals For8-bits Mcus, 3v
• Manufacturer: STMicroelectronics

PSD813F2V, PSD854F2V
Table 20. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
Table 21. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
54/109
MCU I/O
PLD I/O
Data Port (Port A)
Address Out
(Port A,B)
Address In
(Port A,B,C,D)
Peripheral I/O
(Port A)
JTAG ISP (Note
8051XA (8-Bit)
80C251
(Page Mode)
All Other
8-Bit Multiplexed
8-Bit
Non-Multiplexed Bus
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
3. Any of these three methods enables the JTAG pins on Port C.
term (.oe) from the CPLD AND Array.
Mode
MCU
3
)
Declare pins only
Logic equations
N/A
Declare pins only
Logic for equation
Input Macrocells
Logic equations
(PSEL0 & 1)
JTAGSEL
N/A
N/A
Address a3-a0
N/A
Port A (PA3-PA0)
Defined in
1
PSDabel
N/A
N/A
Specify bus type
N/A
N/A
N/A
JTAG
Configuration
Doc ID 10552 Rev 3
Defined in PSD
Configuration
1
Address a7-a4
N/A
Address a7-a4
N/A
Port A (PA7-PA4)
N/A
0
N/A
1
N/A
N/A
N/A
Register
Control
Setting
Address a11-a8
Address a11-a8
Address a3-a0
Address a3-a0
Port B (PB3-PB0)
1 = output,
0 = input
(Note
(Note
N/A
1 (Note
N/A
N/A
N/A
Direction
Register
Setting
2
2
)
)
2
)
N/A
N/A
N/A
N/A
N/A
PIO bit = 1 N/A
N/A
Register
Setting
VM
N/A
Address a15-a12
Address a7-a4
Address a7-a4
Port B (PB7-PB4)
N/A
N/A
N/A
N/A
N/A
JTAG_Enable
JTAG Enable