ht82j31a Holtek Semiconductor Inc., ht82j31a Datasheet - Page 27

• Manufacturer Part Number: ht82j31a
• Description: 16 Channel A/d Mcu With Spi Interface
• Manufacturer: Holtek Semiconductor Inc.

WDT1 is used to clear the WDT, successive executions
of this instruction will have no effect, only the execution
of a CLR WDT2 instruction will clear the WDT. Similarly
after the CLR WDT2 instruction has been executed,
only a successive CLR WDT1 instruction can clear the
Watchdog Timer.
SPI Serial Interface
The device includes two SPI Serial Interfaces. The SPI
interface is a full duplex serial data link, originally de-
signed by Motorola, which allows multiple devices con-
nected to the same SPI bus to communicate with each
other. The devices communicate using a master/slave
technique where only the single master device can initi-
ate a data transfer. A simple four line signal bus is used
for all communication.
SPI Interface Communication
Four lines are used for SPI communication known as
SDI - Serial Data Input, SDO - Serial Data Output, SCK -
Serial Clock and SCS - Slave Select. Note that the con-
dition of the Slave Select line is conditioned by the
CSEN bit in the SBCR control register. If the CSEN bit is
high then the SCS line is active while if the bit is low then
the SCS line will be in a floating condition. The following
timing diagram depicts the basic timing protocol of the
SPI bus.
SPI Registers
There are two registers associated with the SPI Inter-
face. These are the SBCR register which is the control
register and the SBDR which is the data register. The
Rev. 1.00
SPI Block Diagram
27
SBCR register is used to setup the required setup pa-
rameters for the SPI bus and also used to store associ-
ated operating flags, while the SBDR register is used for
data storage.
After Power on, the contents of the SBDR register will be
in an unknown condition while the SBCR register will de-
fault to the condition below:
Note that data written to the SBDR register will only be
written to the TXRX buffer, whereas data read from the
SBDR register will actual be read from the register.
SPI Bus Enable/Disable
To enable the SPI bus and CSEN=1, the SCK, SDI,
SDO and SCS lines should all be zero, then wait for data
to be written to the SBDR (TXRX bufffer) register. For
the Master Mode, after data has been written to the
SBDR (TXRX buffer) register then transmission or re-
ception will start automatically. When all the data has
been transferred the TRF bit should be set. For the
Slave Mode, when clock pulses are received on SCK,
data in the TXRX buffer will be shifted out or data on SDI
will be shifted in.
To Disable the SPI bus SCK, SDI, SDO, SCS floating.
SPI Operation
All communication is carried out using the 4-line inter-
face for both Master or Slave Mode. The timing diagram
shows the basic operation of the bus.
CKS M1 M0 SBEN MLS CSEN WCOL TRF
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