as7c33256ntf3236a ETC-unknow, as7c33256ntf3236a Datasheet - Page 4

• Manufacturer Part Number: as7c33256ntf3236a
• Manufacturer: ETC-unknow

Functional description
The AS7C33256NTF32A/36A family is a high performance CMOS 8 Mbit Synchronous Static Random Access Memory (Flowthrough
SRAM) organized as 262,144 words × 32 or 36 bits and incorporates a LATE Write.
This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD
that improves bandwidth over pipelined burst devices. In a normal flowthrough burst device, the write data, command, and address are all
applied to the device on the same clock edge. If a read command follows this write command, the system must wait for one 'dead' cycle for
valid data to become available. This dead cycle can significantly reduce overall bandwidth for applications requiring random access or read-
modify-write operations.
NTD
Write data is applied one cycle after the write command and address, allowing the read pipeline to clear. With NTD
operations can be used in any order without producing dead bus cycle.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device one clock
cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select,
R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations,
including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33256NTF32A and AS7C33256NTF36A operate with a 3.3V ± 5% power supply for the device core (V
separate power supply (V
Capacitance
* Guaranteed not tested
TQFP thermal resistance
1 This parameter is sampled
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
11/8/04, v. 1.1
™
devices use the memory bus more efficiently by introducing a write latency which matches one-cycle flow-through read latency.
Parameter
Description
1
1
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
Symbol
C
C
I/O
IN
*
*
Conditions
Alliance Semiconductor
Test conditions
V
in
V
= V
in
= 0V
out
= 0V
®
™
1–layer
4–layer
) architecture, featuring an enhanced write operation
Min
-
-
Symbol
θ
θ
θ
JA
JA
JC
AS7C33256NTF32A
AS7C33256NTF36A
Typical
Max
DD
5
7
40
22
8
). DQ circuits use a
™
, write and read
P. 4 of 18
Unit
Units
°C/W
°C/W
°C/W
pF
pF