hi-3210 Holt Integrated Circuits, Inc., hi-3210 Datasheet - Page 26

• Manufacturer Part Number: hi-3210
• Description: Arinc 429 Data Management Engine / Octal Receiver / Quad Transmitter
• Manufacturer: Holt Integrated Circuits, Inc.

After power-on, the HI-3210 is in an undefined state. The
RESET pin must be taken high to begin device
initialization. The RESET pin may be asserted at any
time. Taking RESET high immediately stops all execution
and sets the READY output low indicating that the part is
in the reset state.
On the falling edge of RESET, the HI-3210 samples the
state of the MODE2-0 input pins. This is the only
occasion these inputs are sampled. The state of the
MODE pins determines one of six possible initialization
sequences as shown in the following diagram. These six
initialization modes allow the user to customize the start-
up configuration of the device.
Once the initialization is complete, the device enters the
Idle State when the ready pin goes high. In Idle State, the
host CPU may communicate with the HI-3210 memory
and registers using the host CPU SPI link. When in the
Idle State, the HI-3210 does not transmit or receive any
messages on any of the ARINC 429 buses.
To begin data bus operation, the user must transition the
RUN input from a low to high state. Immediately following
the rising edge of RUN, the part enters the Active State
and bus message processing begins.
During initialization, various device configuration tasks
are performed according to the Mode selection set at the
MODE2:0 input pins. The available options are:
1. RAM Integrity Check
In Modes 2 and 3, the HI-3210 performs a RAM integrity
check. A read/write check is performed on the entire
RAM space. An incrementing pattern is written to
sequential RAM locations then this pattern is read and
verified. Each RAM location is re-written with the 1s
complement of its current contents then this pattern is
read and verified. The incrementing pattern followed by
its 1s complement ensures that each RAM location can
store both a 1 and 0 state. If the RAM integrity check
fails, the MINT pin is asserted and the Pending Interrupt
Register RAMFAIL bit is set. T
state, in which the HI-3210 is able to accept and respond
to Host CPU SPI Instructions, but cannot enter Normal
Operating mode until the RESET input is taken high to
repeat the initialization sequence.
is not maskable.
2. Clear Data Memory
In Modes 0, 1, 2, 3 and 5, the HI-3210 automatically
clears all memory locations in the address range 0x0000
to 0x33FF. This is the space reserved for ARINC 429
message data. Configuration tables and HI-3210
registers are not affected.
RESET AND START-UP
OPERATION
he part enters the “Safe”
The RAMFAIL Interrupt
HOLT INTEGRATED CIRCUITS
HI-3210
26
3. Initialize Registers and Clear all memory
In addition to clearing data memory (0x0000 to 0x33FF),
Modes 0, 1, 2, and 3 also clear all configuration and look-
up tables (0x3400 to 0x7FFF) as well as setting all
registers (0x8000 to 0x807F) to their default states. All
registers default to zero unless otherwise noted.
4. Auto-Initialize from EEPROM
The contents of the Auto-Initialization EEPROM are
copied into the HI-3210 memory and registers via the
EEPROM SPI interface. The part verifies the integrity of
the data transfer from the EEPROM by running through a
byte-by-byte compare routine and a checksum validation.
If a compare error is detected, the AUTOERR bit is set in
the Pending Interrupt Register, the MINT output is
asserted, the location of the error is captured in the
AUTO-INIT FAIL ADDRESS registers 0x8073 (Auto-Init
Fail LS address) and 0x8074 (Auto-Init Fail MS address)
and the part enters the Safe state. If a checksum error is
detected, the CHKERR bit is set in the Pending Interrupt
Register, the MINT output is asserted and the part enters
the Safe state. The AUTOERR and the CHKERR
interrupts are not maskable.
Once initialization is complete, the part enters the Idle
state. The host CPU may read and write HI-3210 internal
memory and registers in all Modes. If not using the auto-
initizarion feature, the host CPU should configure the
device at this time.
NOTE:
used.
Modes 6 and 7 are reserved and should not be