m66014fp Renesas Electronics Corporation., m66014fp Datasheet - Page 3

• Manufacturer Part Number: m66014fp
• Description: 16-bit Serial Bus Controller
• Manufacturer: Renesas Electronics Corporation.

M66014FP
Serial Data Input/Output Operation
A cycle of 16-bit serial output data setting and serial data communication starts with a write access given by
microcomputer to transmission shift registers in M66014.
M66014 has two 8-bit shift registers, on for upper byte (SR
"L" to "H" after a write access is given to SR
are output in series in this order. Output of each data starts from its most significant bit.
At the CS rise edge, busy flag in M66014 is set, and OE output shifts from "H" to "L". Shift clock SCLK and serial data
SOUT are then output.
At SCLK fall edges, serial output shift register executes shifting operation, and data on shift register is output in series
from pin SOUT. Serial input data from pin SIN is taken into input shift register at SCLK rise edges.
After the SCLK 16T rise edge, the status of SOUT and OE shifts to "H" after one bit's delay of SCLK, and busy flag is
reset. When interrupt output is being set to enable, INT output is set.
Remarks
(1) If CS rises after write operation is executed on SR
(2) When write operations executed on SR
Busy flag
REJ03F0265-0200 Rev.2.00 Mar 18, 2008
Page 3 of 4
(in M66014)
SRL
write operation
detection of CS rise. However, if a read access is given after data is written on SR
level, this standby status is canceled. To resume serial communication in this case, rewrite data on SR
CS
OE
INT
SCLK
SOUT
SIN
1T
(D7
DO
DI
15
15
U
)
2T
DO
DI
14
14
Figure 1 Serial Communication Timing Chart
DO
DI
13
13
DO
DI
12
12
L
, M66014 becomes ready for start of serial communication and stands by for
DO
DI
L
, serial data communication is started. SR
11
11
DO
DI
Serial communication period
10
10
L
DO
only and not on SR
DI
9
9
U
8T
(D0
DO
), the other for lower byte (SR
DI
8
U
8
)
9T
(D7
DO
DI
7
7
L
)
DO
DI
6
6
U
, SR
DO
DI
5
5
U
data is unstable.
DO
DI
4
4
L
while CS is maintained on "L"
U
DO
DI
8-bit data and SR
3
3
L
). If the CS status rises from
DO
DI
2
2
DO
DI
1
1
16T
(D0
DO
DI
L
0
L
0
L
and raise CS.
)
8-bit data