lxt362 Intel Corporation, lxt362 Datasheet - Page 24

• Manufacturer Part Number: lxt362
• Description: Integrated T1 Lh/sh Transceiver For Ds1/dsx-1 Or Pri Applications
• Manufacturer: Intel Corporation

LXT362 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.7.2
2.7.2.1
2.7.2.2
24
Figure 9. Dual Loopback
Figure 10. TAOS Data Path
Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data and clock recovered
from the twisted-pair line loop back through the transmit circuits to TTIP and TRING without jitter
attenuation.
Internal Pattern Generation and Detection
Transmit All Ones (TAOS)
See
transmits a continuous stream of 1’s at the TCLK frequency. When TCLK is not supplied, TAOS
timing is derived from MCLK. This can be used as the Alarm Indication Signal (AIS–also called
the Blue Alarm).
Both TAOS and LLOOP can operate simultaneously as shown in
inhibits TAOS. When both TAOS and LLOOP are active, TCLK and TPOS/TNEG loop back to
RCLK and RPOS/RNEG (through the jitter attenuator if enabled), and the all ones pattern is also
routed to TTIP/TRING.
In Host mode, TAOS is activated when bit CR2.ETAOS = 1. In Hardware mode, setting the TAOS
pin High activates TAOS.
Quasi-Random Signal Source (QRSS)
See
(PRBS) with no more than 14 consecutive zeros.
Both Hardware and Host Modes allow QRSS mode. The QRSS pattern is normally locked to
TCLK, however, if there is no TCLK, MCLK is the clock source. Bellcore Pub 62411 defines the
T1 QRSS transmit format.
Figure
Figure
10. When TAOS is active, the transceiver ignores the TPOS and TNEG inputs and
11. The Quasi-Random Signal Source (QRSS) is a 2
RNEG
RNEG
RPOS
TNEG
RPOS
TPOS
RCLK
TPOS
TNEG
RCLK
TAOS
TCLK
TCLK
JA*
* If Enabled
Timing &
Recovery
Control
* If Enabled
Timing
Recovery
Timing &
Control
Timing
20
Figure
-1 pseudo-random bit sequence
TRING
TTIP
RTIP
RRING
TTIP
TRING
RTIP
RRING
5, however, RLOOP
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