DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 12

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Preliminary data sheet
Fig 3.
SYNC_OUT
lane#
The descrambler can be enabled/disabled
JESD204A receiver
DES
10.2 JESD204A receiver
10b
The JEDEC204A defines the following parameters:
The DAC1408D650 supports both LMF = 421 and LMF = 211. The current setting is
configurable via the SPI registers interface.
The complete Digital Layer Processing (DLP) adds a variable delay on each lane path.
This is mainly because of the interlane alignment.
Table 6.
[1]
[2]
Symbol Parameter
t
d
CLOCK
ALIGN
frame
clock
D = guaranteed by design.
Frame clock cycle.
10b
delay time
Digital Layer Processing Latency
L is the number of lanes per link
M is the number of converters per device
F is the number of bytes per frame clock period
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
WORD
ALIGN
SYNC
All information provided in this document is subject to legal disclaimers.
AND
Conditions
digital layer processing
delay
Rev. 02 — 11 August 2010
10b
K-DETECT
10b/8b
RX CONTROLLER
8b
DESCRAMBLER
Test
D
[1]
8b
Min
13
DAC1408D650
Typ
-
8b
8b
8b
8b
© NXP B.V. 2010. All rights reserved.
Max
28
14b
14b
configuration
interface
internal
001aak161
Unit
Cycle
12 of 98
[2]