DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 20

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Preliminary data sheet
10.2.5.4 All slave mode
The external reference is provided by the JESD204A transmitter. All DACs are configured
in Slave mode.
The MDS signal is now driven from the transmitter. It is generated at the end of the
interlane alignment phase (see the JESD204A standard for details).
The transmitter must also compensate for the DAC latency. Although the DAC has an
internal samples delay line, it cannot handle large delays.
In this mode, PCB layout is also important. The following delay equation applies:
δt
Fig 12. All slave mode
<
Δt
mds
INSERTION
/A/
<
TDAC δt
Jesd204A
TX
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
dT
–
Rev. 02 — 11 August 2010
, where δt is the clock skew considered close to DAC pins.
MDS
SYNC_0
SYNC_1
SYNC_2
DIG
DIG
DIG
ref_A
ref_A
ref_A
BUFFER
BUFFER
BUFFER
COMP
MGMT
COMP
MGMT
COMP
MGMT
CLK
CLK
CLK
mds_out
mds_out
mds_out
mds_in
mds_in
mds_in
DAC_0
DAC_1
DAC_2
Q
Q
Q
I
I
I
DAC1408D650
DISTRIBUTION
CLOCK
© NXP B.V. 2010. All rights reserved.
SLAVE
SLAVE
SLAVE
DAC 0
DAC 1
DAC 2
REF_CLOCK
001aal069
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