HYB18H512321BF-08/10 QIMONDA [Qimonda AG], HYB18H512321BF-08/10 Datasheet - Page 21
HYB18H512321BF-08/10
Manufacturer Part Number
HYB18H512321BF-08/10
Description
512-Mbit GDDR3 Graphics RAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1.HYB18H512321BF-0810.pdf
(43 pages)
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4.2.5
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set to 1 and bits
A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3 DRAM will provide the
Qimonda vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will be driven onto the DQ bus after
tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and Revision ID will be driven on DQ[7:0] until a
new EMRS command is issued with A10 set back to 0. After
back to HIGH. This second EMRS command must be issued before initiating any subsequent operation. Violating this
requirement will result in unspecified operation.
Note: Please refer to Revision Release Note for Revision ID value.
Rev. 1.1, 2007-09
05292007-WAU2-UU95
Revision Identification
DQ[7:4]
0011
DQ[7:0]
A[9:0],
A11
CLK#
Com.
RDQS
CLK
A10
Vendor Code and Revision Identification
EMRS
Add
0
N/D
1
t
RIDon
N/D
2
N/D
3
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
N/D
4
t
RDoff
21
Qimonda Vendor Code
DQ[3:0]
0010
N/D
5
following the second EMRS command, the data bus is driven
Vendor Code and Revision ID
EMRS
Add
6
N/D
7
t
RIDoff
EMRS: Extended Mode Register Set Command
Add:
N/D:
N/D
8
Don't Care
NOP or Deselect
Address
Revision ID and Vendor Code
N/D
9
N/D
10
Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
FIGURE 10
TABLE 10
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