GS880V37AT GSI [GSI Technology], GS880V37AT Datasheet - Page 5

• Manufacturer Part Number: GS880V37AT
• Description: 256K x 36 9Mb Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Notes:
1.
2.
3.
Rev: 1.03 7/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
1st address
4th address
Write all bytes
Write all bytes
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Write byte a
Write byte b
Write byte c
Write byte d
Function
Read
Read
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
GW
H
H
H
H
H
H
H
L
A
, B
01
10
00
11
B
, B
C
and/or B
Name
BW
10
11
00
01
LBO
H
Pin
L
L
L
L
L
L
X
ZZ
D
may be used in any combination with BW to write single or multiple bytes.
00
01
10
11
L or NC
State
H
H
L
B
H
X
H
H
H
X
L
L
A
5/18
B
Standby, I
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
X
H
H
H
H
X
L
L
B
Linear Burst
Function
2nd address
3rd address
4th address
1st address
Active
DD
= I
B
X
H
H
H
H
X
L
L
SB
C
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
B
X
H
H
H
H
X
L
L
D
GS880V37AT-250/225/200
01
00
11
10
Notes
10
00
01
11
2, 3
2, 3
2, 3
2, 3
2, 3
1
1
© 2002, GSI Technology
11
10
01
00
BPR 1999.05.18