MC14490DWR2G ON Semiconductor, MC14490DWR2G Datasheet - Page 5

• Manufacturer Part Number: MC14490DWR2G
• Description: IC ELIMINATOR BOUNCE HEX 16-SOIC
• Manufacturer: ON Semiconductor
• Series: 4000r

Specifications of MC14490DWR2G

• Logic Type: Contact Bounce Eliminator
• Supply Voltage: 3 V ~ 18 V
• Number Of Bits: 6
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Function: Eliminator
• Operating Temperature (max): 125C
• Operating Temperature (min): -55
• Package Type: SOIC W
• Pin Count: 16
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Number Of Circuits: Hex
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC14490DWR2G; MC14490DWR2GOSTR

basically a digital integrator. The circuit can integrate both
up and down. This enables the circuit to eliminate bounce on
both the leading and trailing edges of the signal, shown in the
timing diagram of Figure 3.
4−1/2−bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in
Figure 4. The shift register requires a series of timing pulses
in order to shift the input signal into each shift register
location. These timing pulses (the clock signal) are
represented in the upper waveform of Figure 3. Each of the
six Bounce Eliminator circuits has an internal resistor as
shown in Figure 4. A pullup resistor was incorporated rather
than a pulldown resistor in order to implement switched
ground input signals, such as those coming from relay
contacts and push buttons. By switching ground, rather than
a power supply lead, system faults (such as shorts to ground
on the signal input leads) will not cause excessive currents
in the wiring and contacts. Signal lead shorts to ground are
much more probable than shorts to a power supply lead.
level is inverted, and the shift register is loaded with a high
on each positive edge of the clock signal. To understand the
operation, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
high has been loaded into the first bit or storage location of
the shift register. Just after the positive edge of clock 1, the
input signal has bounced back to a high. This causes the shift
register to be reset to lows in all four bits — thus starting the
timing sequence over again.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
period delay between the clean input signal and output
signal. In this example there is a delay of 3.8 clock periods
from the beginning of the clean input signal.
The MC14490 Hex Contact Bounce Eliminator is
Each of the six Bounce Eliminators is composed of a
When the relay contact is closed, (see Figure 4) the low
At clock edge 1 (Figure 3) the input has gone low and a
During clock edges 3 to 6 the input signal has stayed low.
It should be noted that there is a 3−1/2 to 4−1/2 clock
OSC
in
OR OSC
CONTACT
OUTPUT
OPEN
INPUT
out
1
BOUNCING
CONTACT
2
3
(VALID TRUE SIGNAL)
4
CONTACT CLOSED
THEORY OF OPERATION
Figure 3. Timing Diagram
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6
5
opened and at N+1 a low is loaded into the first bit. Just after
N+1, when the input bounces low, all bits are set to a high.
At N +2 nothing happens because the input and output are
low and all bits of the shift register are high. At time N +3
and thereafter the input signal is a high, clean signal. At the
positive edge of N+6 the output goes high as a result of four
lows being shifted into the shift register.
through the Bounce Eliminator, the output signal will be no
longer or shorter than the clean input signal plus or minus
one clock period.
output signals is a function of the difference in bounce
characteristics on the edges of the input signal and the clock
frequency. Since most relay contacts have more bounce
when making as compared to breaking, the overall delay,
counting bounce period, will be greater on the leading edge
of the input signal than on the trailing edge. Thus, the output
signal will be shorter than the input signal — if the leading
edge bounce is included in the overall timing calculation.
obtain a bounce free output signal is that four clock periods
do not occur while the input signal is in a false state.
Referring to Figure 3, a false state is seen to occur three times
at the beginning of the input signal. The input signal goes
low three times before it finally settles down to a valid low
state. The first three low pulses are referred to as false states.
frequency, it may be used by connecting it to the oscillator
input (pin 7). However, if an external clock is not available
the user can place a small capacitor across the oscillator
input and output pins in order to start up an internal clock
source (as shown in Figure 4). The clock signal at the
oscillator output pin may then be used to clock other
MC14490 Bounce Eliminator packages. With the use of the
MC14490, a large number of signals can be cleaned up, with
the requirement of only one small capacitor external to the
Hex Bounce Eliminator packages.
N + 1
After some time period of N clock periods, the contact is
Assuming the input signal is long enough to be clocked
The amount of time distortion between the input and
The only requirement on the clock frequency in order to
If the user has an available clock signal of the proper
BOUNCING
CONTACT
N + 3
CONTACT OPEN
N + 5
N + 7