MC3PHACVPE Freescale Semiconductor, MC3PHACVPE Datasheet - Page 13

IC MOTOR CONTROLLER 28-DIP

MC3PHACVPE

Manufacturer Part Number
MC3PHACVPE
Description
IC MOTOR CONTROLLER 28-DIP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC3PHACVPE

Applications
AC Motor Controller, 3 Phase
Number Of Outputs
1
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Through Hole
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
MC3PHAC
Core
HC08
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
256 KB
Interface Type
RS-232
Maximum Clock Frequency
21.16 KHz
Number Of Programmable I/os
14
Number Of Timers
1
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Controller Family/series
HC08
Core Size
8 Bit
Ram Memory Size
256Byte
Embedded Interface Type
SCI
Digital Ic Case Style
DIP
No. Of Pins
28
A/d Converter
10 Bits
No. Of Timers 8/12/16/32 Bits
0/0/2/0
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output
-
Voltage - Load
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC3PHACVPE
Manufacturer:
TE
Quantity:
1 001
logic, and can cause the device to malfunction. The same noise spike applied to the input of a PLL clock
circuit is perceived by the PLL as a change in its reference frequency, and the PLL output frequency
begins to change in an attempt to lock on to the new frequency. However, before any appreciable change
can occur, the spike is gone, and the PLL settles back into the true reference frequency.
Fault Protection — The MC3PHAC supports an elaborate range of fault protection and prevention
features. If a fault does occur, the MC3PHAC immediately disables the PWMs and waits until the fault
condition is cleared before starting a timer to re-enable the PWMs. Refer to the graph in
resistance value versus retry time.
timeout interval is specified during the initialization phase by supplying a voltage to the MUX_IN pin while
the RETRY_TxD pin is being driven low. In this way, the retry time can be specified from 1 to 60 seconds,
with a scaling factor of 12 seconds per volt. In PC master software mode, the retry time can be specified
from 0.25 second to over 4.5 hours and can be changed at any time.
The fault protection and prevention features are:
Freescale Semiconductor
External Fault Monitoring — The FAULTIN pin accepts a digital signal that indicates a fault has
been detected via external monitoring circuitry. A high level on this input results in the PWMs being
immediately disabled. Typical fault conditions might be a dc bus over voltage, bus over current, or
over temperature. Once this input returns to a logic low level, the fault retry timer begins running,
and PWMs are re-enabled after the programmed timeout value is reached.
Lost Clock Protection — If the signal on the OSC1 pin is lost altogether, the MC3PHAC will
immediately disable the PWM outputs to protect the motor and power electronics. This is a special
fault condition in that it will also cause the MC3PHAC to be reset. Lost clock detection is an
important safety consideration, as many safety regulatory agencies are now requiring a dead
crystal test be performed as part of the certification process.
Low V
reset the MC3PHAC. This allows the MC3PHAC to operate properly with 5 volt power supplies of
either 5 or 10 percent tolerance.
Bus Voltage Integrity Monitoring — The DC_BUS pin is monitored at a 5.3 kHz frequency
(4.0 kHz when the PWM frequency is set to 15.9 kHz), and any voltage reading outside of an
acceptable window constitutes a fault condition. In standalone mode, the window thresholds are
fixed at 4.47 volts (128 percent of nominal), and 1.75 volts (50 percent of nominal), where nominal
is defined to be 3.5 volts. In PC master software mode, both top and bottom window thresholds can
be set independently to any value between 0 volts (0 percent of nominal), and greater than 5 volts
(143 percent of nominal), and can be changed at any time. Once the DC_BUS signal level returns
to a value within the acceptable window, the fault retry timer begins running, and PWMs are re-
enabled after the programmed timeout value is reached.
During power-up, it is possible that V
charges up to its nominal value. When the dc bus integrity is checked, an under voltage would be
detected and treated as a fault, with its associated timeout period. To prevent this, the MC3PHAC
monitors the dc bus voltage during power-up in standalone mode, and waits until it is higher than
the under voltage threshold before continuing. During this time, all MC3PHAC functions are
suspended. Once this threshold is reached, the MC3PHAC will continue normally, with any further
under voltage conditions treated as a fault.
If dc bus voltage monitoring is not desired, a voltage of 3.5 volts ± 5 percent should be supplied to
the DC_BUS pin through an impedance of between 4.7 kΩ and 15 kΩ.
DD
Protection — Whenever V
MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2
Figure 10
DD
DD
assumes a 6.8 kΩ pullup resistor. In standalone mode, this
could reach operating voltage before the dc bus capacitor
falls below V
LVR1
, an on-board power supply monitor will
Figure 10
Features
for the
13

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