ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 41
ATTINY20-EK1
Manufacturer Part Number
ATTINY20-EK1
Description
KIT EVAL TOUCH ATTINY20
Manufacturer
Atmel
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-EK1
Sensor Type
*
Sensing Range
*
Interface
*
Sensitivity
*
Voltage - Supply
*
Embedded
*
Utilized Ic / Part
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
TinyAVR
Kit Contents
Board
Svhc
No SVHC (15-Dec-2010)
Mcu Supported Families
ATtiny20
Tool / Board Applications
Microcontroller
Rohs Compliant
Yes
Tool Type
Development Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor To Be Evaluated
ATtiny20
Interface Type
Touch
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.3
9.3.1
9.3.2
8235B–AVR–04/11
Register Description
MCUCR – MCU Control Register
GIMSK – General Interrupt Mask Register
The MCU Control Register contains bits for controlling external interrupt sensing and power
management.
• Bits 7:6 – ISC01, ISC00: Interrupt Sense Control
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT[11:8] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT[11:8] pins are enabled individually by the PCMSK1 Register.
• Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register.
Bit
0x3A
Read/Write
Initial Value
Bit
0x0C
Read/Write
Initial Value
ISC01
0
0
1
1
ISC01
Interrupt 0 Sense Control
R/W
ISC00
7
0
R
7
–
0
0
1
0
1
ISC00
R/W
Table
6
0
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
R
6
–
0
9-2. The value on the INT0 pin is sampled before detecting edges.
R
5
–
0
PCIE1
R/W
5
0
BODS
R/W
4
0
PCIE0
R/W
4
0
SM2
R/W
3
0
R
3
–
0
SM1
R/W
2
0
R
2
–
0
SM0
R/W
1
0
R
1
–
0
R/W
SE
0
0
ATtiny20
INT0
MCUCR
R/W
0
0
GIMSK
41
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