CA3059 Intersil, CA3059 Datasheet - Page 10

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CA3059

Manufacturer Part Number
CA3059
Description
ZERO VOLTAGE CROSSING SWITCH
Manufacturer
Intersil
Datasheet

Specifications of CA3059

Rohs Status
RoHS non-compliant

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The circuit shown in Figure 19 forms a pulse of gate current
and can supply high peak drive to power triacs with low aver-
age current drain on the internal supply. The gate pulse will
always last just long enough to latch the thyristor so that
there is no problem with delaying the pulse to an optimum
time. As in other circuits of this type, RFI results if the load is
not suitable inductive because the zero crossing detector is
disabled and initial turn on occurs at random.
The gate pulse forms because the voltage at point A when
the thyristor is on is less than 1.3V; therefore, the output of
the zero-voltage switch is inhibited, as described above.
The resistor divider R
this condition. When the triac is on, the voltage at point A is
approximately one third of the instantaneous on state
voltage (V
less than 2V, and the divider shown is a conservative one.
When the load current passes through zero, the triac
commutates and turns off. Because the circuit is still being
driven by the line voltage, the current in the load attempts to
reverse, and voltage increases rapidly across the “turned-
off” triac. When this voltage exceeds 4V, one portion of the
CA3086 conducts and removes the inhibit signal to permit
application of gate drive. Turning the triac on causes the
voltage across it to drop and thus ends the gate pulse. If the
latching current has not been attained, another gate pulse
forms, but no discontinuity in the load current occurs.
50-60Hz
FIGURE 19. USE OF THE CA3059 TOGETHER WITH 3086 FOR
120V
SENSOR
AC
NTC
R
T
P
) of the thyristor. For most thyristors, V
SWITCHING INDUCTIVE LOADS
Q
100/12V
+
14
13
5
13
2
1
and R
12
12
5
Q
4
ZVS
5K
4W
11
10
9
7
2
should be selected to assure
10
8
4
11
1
5
3
39K
CA3086
Q
R
4
2
3
6
INDUCTIVE
Q
7
8
Application Note 6182
G
3
LOAD
T
MT
MT
20K
9
1W
R
(max) is
2
1
1
10K
A
R
2
10
Provision of Negative Gate Current
Triacs trigger with optimum sensitivity when the polarity of
the gate voltage and the voltage at the main terminal 2 are
similar (I+ and II- modes). Sensitivity is degraded when the
polarities are opposite (I- and III+ modes). Although Intersil
triacs are designed and specified to have the same
sensitivity in both I- and III+ modes, some other types have
very poor sensitivity in the III+ condition. Because the
zero-voltage switch supplies positive gate pulses, it may
not directly drive some high current triacs of these other
types.
The circuit shown in Figure 20A. uses the negative going
voltage at terminal 3 of the zero-voltage switch to supply a
negative gate pulse through a capacitor. The curve in Figure
20B. shows the approximate peak gate current as a function
of gate voltage V
120V
FIGURE 20. USE OF THE CA3059 TO PROVIDE NEGATIVE
60Hz
AC
+
-
100 F
15V
DC
30
20
10
40
0
0
G
R
NTC
SENSOR
P
. Pulse width is approximately 80 s.
GATE VOLTAGE (V
FIGURE 20A.
FIGURE 20B.
V
S
-1
14
13
2
8
7
5
9
CA3059
V
R
10
6
-2
G
) (V)
11
1
12
R
3
L
50 F
10V
4
-3
-
G
MT
MT
2
1

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