AD7878 AD [Analog Devices], AD7878 Datasheet
AD7878
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AD7878 Summary of contents
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... FIFO and contains the FIFO out of range, FIFO empty and FIFO word count information. The analog input of the AD7878 has a bipolar range The AD7878 can convert full power signals kHz and is fully specified for dynamic parameters such as signal-to-noise ratio and harmonic distortion ...
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... AD7878–SPECIFICATIONS Parameter 2 DYNAMIC PERFORMANCE 3 Signal-to-Noise Ratio (SNR MIN MAX Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Track/Hold Acquisition Time DC ACCURACY Resolution Minimum Resolution for Which No Missing Codes are Guaranteed ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7878 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Active Low Logic Output. This output goes low when the ADC receives a CONVST pulse and remains low until the track/hold 15 has gone into its hold mode. The three-state drivers of the AD7878 can be disabled while the BUSY signal is low (see Extended READ/WRITE section). This is achieved by writing a logic 0 to DB5 (DISO) of the status/control register. Writing a logic 1 to DB5 of the status/control register allows data to be accessed from the AD7878 while BUSY is low ...
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... AD7878BQ – + AD7878LN + AD7878SE – +125 AD7878JP + AD7878KP + AD7878LP + NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. ...
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... Each word in memory contains 13 bits of information—12 bits of data from the conversion result and one additional bit which contains information as to whether the 12- bit result is out of range or not. A block diagram of the AD7878 FIFO architecture is shown in Figure 3. Figure 3. Internal FIFO Architecture The conversion result is gathered in the successive approxima- tion register (SAR) during conversion ...
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... This may result in shorter write pulse widths, data setup times and data hold times than those given by the microprocessor. The timing on the AD7878 timing diagram of Figure 8 is there- fore given with respect to the internal REGISTER ENABLE signal rather than the DMWR signal. ...
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... When CONVST goes low, the AD7878 acknowledges it by bringing BUSY low on the next rising edge of CLK IN. With a logic 0 in DB5, the AD7878 data bus cannot now be enabled read/write operation now occurs, the BUSY and CS gated signal drives the microprocessor into a WAIT state, thereby extending the read/write operation ...
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... REV. A Histogram Plot When a sine wave of a specified frequency is applied to the V input of the AD7878 and several million samples are taken possible to plot a histogram showing the frequency of occur- rence of each of the 4096 ADC codes particular step is 2 ...
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... Where adjustment is required, offset must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7878 while the input voltage is 1/2 LSB below ground. The trim procedure is as follows: apply a voltage of –0.73 mV (–1/2 LSB adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000 ...
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... Figure 19. AD7878–TMS32020 Interface The interfaces to the ADSP-2100 and the TMS32020 gate the AD7878 CS and the BUSY to provide a signal which drives the processor into a wait state if a read/write operation to the ADC is attempted while the ADC track/hold amplifier is going from the track to the hold mode. This avoids digital feedthrough to the analog circuitry ...
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... FIFO memory locations to be read and the software organization example, consider an application using the ADSP-2100 and the AD7878 with a throughput rate of 100 kHz. The time required for the CONVST pulse and the ADC conversion is 7.375 s. This leaves 2.625 s for the track/hold acquisition time and for reading the ADC (both operations occurring in parallel) ...
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... ADSP-2100 Evaluation Board Prototype Expansion Con- nector. The expansion connector on the ADSP-2100 has eight decoded drip enable outputs labelled ECE8 to ECE1. ECE6 is used to drive the AD7878 CS input on the data acquisition board. To avoid selecting onboard RAM sockets at the same time, LK6 on the ADSP-2100 board must be removed. In addi- tion, the expansion connector on the ADSP-2100 has four inter- REV ...
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... AD7878 Figure 23. Data Acquisition Circuit Using the AD7878 Figure 24. PCB Silkscreen for Figure 23 –14– REV. A ...
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... Figure 25. PCB Component Side Layout for Figure 23 REV. A Figure 26. PCB Solder Side Layout for Figure 23 –15– AD7878 ...
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... AD7878 Table IV. TMS32010/TMS32020 Interface Connections IDC Signal Connect TMS32010 Contact No. Mnemonic Signal 1 R/W — STRB 2 — DMRD DEN 3 DMWR READY — RESET RESET 7 ALFL INT 8 9 ADD0 PA0 10 CLK CLKOUT 11 DB10 D10 12 DB11 D11 13 DB8 D8 14 DB9 D9 15 DB6 ...