ics673-01 Integrated Device Technology, ics673-01 Datasheet
ics673-01
Related parts for ics673-01
ics673-01 Summary of contents
Page 1
... VCO dividers (the ICS674-01), the user can customize the clock to lock to a wide variety of input frequencies. The ICS673-01 also has an output enable function that puts both outputs into a high-impedance state. The chip also has a power-down feature which turns off the entire device. ...
Page 2
... Clock output connect. Nothing is connected internally to this pin. Input Reference input. Connect reference clock to this pin. Triggered on falling edge. 2 PLL BUILDING BLOCK SEL VCO Predivide connect pin directly to ground 1 = connect pin directly to VDD Pin Description ICS673-01 REV Q 071906 ...
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... PLL BUILDING BLOCK Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS673-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. ...
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... Avoiding PLL Lockup In some applications, the ICS673-01 can “lock up” at the maximum VCO frequency. This is usually caused by power supply glitches or a very slow power supply ramp. This situation also occurs if the external divider starts to fail at high input frequencies. The usual failure mode of a divider circuit is that the output of the divider begins to miss clock edges ...
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... R2 and R3. The voltage should be set to a value higher than the VCO input is expected to run during normal operation. Typically, this might be 0.5 V below VDD. Hysteresis should be added to the circuit by connecting R4. 5 PLL BUILDING BLOCK ICS673-01 REV Q 071906 ...
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... Figure 3. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference. 0.01 F 200 kHz IDT™ / ICS™ PLL BUILDING BLOCK Explanation of Operation The ICS673- PLL building block circuit that includes an integrated VCO with a wide operating range. The device PD CAP uses external PLL loop filter components which through proper configuration allow for low input clock reference frequencies, such ...
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... PLL BUILDING BLOCK = 1. the nearest standard value used to damp transients from the (56 pF nearest standard value 1 CLK1 CLK2 REFIN CLK2 Feedback CLK1 CLK2 REFIN CLK1 Feedback ICS673-01 REV Q 071906 ...
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... SOIC -40 to +85 C 16-pin SOIC -40 to +85 C 16-pin SOIC -40 to +85 C 16-pin SOIC 0 to +70 C 16-pin SOIC 0 to +70 C 16-pin SOIC 0 to +70 C 16-pin SOIC 0 to +70 C ICS673-01 Inches* Max .0688 .0098 .020 .0098 .3937 .1574 .2440 .020 .050 8 C REV Q 071906 ...
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... ICS673-01 PLL BUILDING BLOCK Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...