ics9fg1201h Integrated Device Technology, ics9fg1201h Datasheet
ics9fg1201h
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ics9fg1201h Summary of contents
Page 1
... DIF_(9:0) can be “gear-shifted” from the input CPU Host Clock DIF_(11:10) can be “gear-shifted” from the input CPU Host Clock Spread spectrum compatible Supports output clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode 2 STOP DIF(11:10) LOGIC 10 STOP DIF(9:0) LOGIC IREF DATASHEET ICS9FG1201H 10/22/07 ...
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... DIF_5 DIF_6# OE5 OE6# SMB_A1 27 30 SMB_A2_PLLBYP# SMBDAT 28 29 SMBCLK 56-pin SSOP & TSSOP DIF_(9:0) Output DIF_(11:10) Output MHz MHz 100.00 100.00 133.33 133.33 166.66 166.66 RESERVED 200.00 200.00 266.66 266.66 333.33 333.33 400.00 400.00 and V IL_FS IH_FS 2 ICS9FG1201H 10/22/07 ...
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... PWR Power supply, nominal 3.3V PWR Ground pin. OUT 0.7V differential true clock output OUT 0.7V differential complement clock output Active low input for enabling DIF pair tri-state outputs enable outputs IN SMBus address bit 1 I/O Data pin of SMBUS circuitry, 5V tolerant 3 ICS9FG1201H 10/22/07 ...
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... This pin establishes the reference current for the differential current- mode output pairs. This pin requires a fixed precision resistor tied to OUT ground in order to establish the appropriate current. 475 ohms is the standard value. PWR Ground pin for the PLL core. PWR 3.3V power for the PLL core. 4 ICS9FG1201H 10/22/07 ...
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... 166.67 66.7 69.4 83.3 100.0 104.2 111.1 133.3 138.9 166.7 200.0 208.3 222.2 277.8 333.3 ICS9FG1201H 10/22/07 ...
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... SMB_A(2:0) = 011 SMB Adr: D6 9FG1201 (DB1200G) SMB_A(2:0) = 100 SMB Adr: D8 9FG1201 (DB1200G) SMB_A(2:0) = 101 SMB Adr: DA 9FG1201 (DB1200G) SMB_A(2:0) = 110 SMB Adr: DC 9FG1201 (DB1200G) SMB_A(2:0) = 111 SMB Adr: DE 9FG1201 (DB1200G) 6 SMB Adr: D2 954101 OR 932S401 (CK410/410B) SMB Adr 9DB104/108 (DB400/800) ICS9FG1201H 10/22/07 ...
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... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks General SMBus serial interface information for the ICS9FG1201H How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D0 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...
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... Type High BW Low BW RW Bypass PLL RW Hi-Z Enable RW Hi-Z Enable RW Hi-Z Enable RW Hi-Z Enable Type Readback R Readback R Readback R Readback R Readback R Readback R Readback R Readback ICS9FG1201H 10/22/07 PWD Latch PWD PWD PWD ...
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... Type Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved Type ICS9FG1201H 10/22/07 PWD PWD PWD PWD ...
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... M Divider Programming bits 10 Type See 9FG1201H 1:1 PLL RW Programming Table RW Type 0 1 Type Disable Enable Type See 9FG1201H M/N RW programming Table ICS9FG1201H 10/22/07 PWD Latch PWD PWD PWD X X ...
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... RESERVED Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED PWD See 9FG1201H M/N X programming Table PWD Table PWD PWD ICS9FG1201H 10/22/07 ...
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... RESERVED RESERVED RESERVED RW See 1:1 Output Divider RW 1:1 Output Divider PWD PWD See 9FG1201H M/N X programming Table PWD See 9FG1201H M/N X programming Table PWD Table X X ICS9FG1201H 10/22/07 ...
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... ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST PWD Test Result PWD RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved RW Reserved ICS9FG1201H 10/22/ ...
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... 0 0.3 0. 400 100 400 MHz 1 kHz 300 5 1000 ns 300 ns ICS9FG1201H 10/22/ ...
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... ICS9FG1201H 10/22/07 1 1 1,2 1,2 1,2 1,2 1,2 1,2 1 1,4,5 1,4 ...
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... Bypass and PLL mode - all outputs at same gear) (HIGH_BW (HIGH_BW (HIGH_BW (HIGH_BW PCIe Gen 1 phase jitter (1 MHz) FBD phase jitter (11-33 MHz) 16 Min Typ Max Units Notes 1,2,4,5,6, -500 500 ps 10 1,2,3,5, 2.5 4 1,2, 1,2,10 100 ps 1,2,3,10 0 2 MHz 10,11 0.7 1.4 MHz 10,11 108 ps 1,7,8, rms 1,7,8,10 ICS9FG1201H 10/22/07 ...
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... Dimension or Value Unit Figure 2 min to 16 max inch 1 1.8 min to 14.4 max inch 1 Dimension or Value Unit Figure 0. max inch 2 0.225 min to 12.6 max inch 2 L4 L4’ PCI Ex Board Down Device REF_CLK Input L4 L4’ PCI Ex Add In Board REF_CLK Input ICS9FG1201H 10/22/07 ...
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... R1a L4’ L2’ R1b R2a R2b L3’ L3 Note 3.3 Volts R5a R5b Cc Cc R6a R6b 18 Figure 3. Note ICS874003i-02 input compatible Standard LVDS R4 Down Device REF_CLK Input PCIe Device REF_CLK Input ICS9FG1201H 10/22/07 ...
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... SEE VARIATIONS SEE VARIATIONS 10.03 10.68 .395 7.40 7.60 .291 0.635 BASIC 0.025 BASIC 0.38 0.64 .015 0.50 1.02 .020 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° D mm. D (inch) MIN MAX MIN 18.31 18.55 .720 ICS9FG1201H 10/22/07 MAX .110 .016 .0135 .010 .420 .299 .025 .040 8° MAX .730 ...
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... E 8.10 BASIC E1 6.00 6.20 e 0.50 BASIC L 0.45 0.75 N SEE VARIATIONS SEE VARIATIONS . 0° 8° aaa -- 0.10 D mm. N MIN MAX 56 13.90 14.10 ICS9FG1201H 10/22/07 In Inches MIN MAX -- .047 .002 .006 .032 .041 .007 .011 .0035 .008 0.319 BASIC .236 .244 0.020 BASIC .018 .030 0° 8° -- .004 D (inch) MIN MAX ...
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... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Revision History Rev. Issue Date Description A 10/22/07 Release to Final. TM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-6578 408-284-8200 pcclockhelp@idt.com Fax: 408-284-2775 ...