IDT5T9304 Integrated Device Technology, IDT5T9304 Datasheet

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IDT5T9304

Manufacturer Part Number
IDT5T9304
Description
2.5v Lvds, 1 4 Clock Buffer Terabuffer? Ii
Manufacturer
Integrated Device Technology
Datasheet

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Part Number:
IDT5T9304EJGI
Manufacturer:
IDT
Quantity:
20 000
2.5V LVDS, 1:4 CLOCK BUFFER
TERABUFFER™ II
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
Description
The IDT5T9304 2.5V differential clock buffer is a user-selectable
differential input to four LVDS outputs. The fanout from a
differential input to four LVDS outputs reduces loading on the
preceding driver and provides an efficient clock distribution
network. The IDT5T9304 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS
input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input
can also be used to translate to LVDS outputs. The redundant
input capability allows for an asynchronous change-over from a
primary clock source to a secondary clock source. Selectable
reference inputs are controlled by SEL.
The IDT5T9304 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the
GL pin. Multiple power and grounds reduce noise.
Applications
Pin Assignment
IDT™ LVDS CLOCK BUFFER TERABUFFER™ II
Clock distribution
4.4mm x 7.8mm x 1.0mm package body
24-Lead TSSOP
GND
GND
SEL
V
V
PD
Q1
Q1
Q2
Q2
nc
DD
DD
G
G Package
Top View
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A2
A2
GND
V
Q3
Q3
Q4
V
GL
A1
DD
DD
1
Features
Guaranteed low skew: 25ps (typical)
Very low duty cycle distortion: 250ps (typical)
High speed propagation delay: 1.7ns (typical)
Up to 450MHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
Selectable differential inputs to four LVDS outputs
2.5V V
-40°C to 85°C ambient operating temperature
Available in TSSOP package
DD
IDT5T9304 REV. A JULY 23, 2007
PRELIMINARY
IDT5T9304

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IDT5T9304 Summary of contents

Page 1

... LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T9304 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs ...

Page 2

... IDT5T9304 2.5V LVDS 1:4 CLOCK BUFFER TERABUFFER™ II Block Diagram SEL IIDT™ LVDS CLOCK BUFFER TERABUFFER™ PRELIMINARY OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL IDT5T9304 REV. A JULY 23, 2007 ...

Page 3

... V Power supply for the device core and inputs. Power supply return for all power. No connect; recommended to connect to GND +25° 1.0MHz) A Test Conditions 3 PRELIMINARY For . (2) . (3) . Set HIGH for normal operation. DD Minimum Typical Maximum 3 IDT5T9304 REV. A JULY 23, 2007 Units pF ...

Page 4

... Ambient Operating Temperature A V Internal Power Supply Voltage DD IIDT™ LVDS CLOCK BUFFER TERABUFFER™ II Outputs Q[1:4] Toggling HIGH Toggling LOW Inputs A2/A2 A1/A1 Rating -0.5V to +3.6V -0.5V to +3.6V -0 -65°C to 150°C 150°C Minimum -40 2.3 4 +0.5V DD Typical Maximum +25 +85 2.5 2.7 IDT5T9304 REV. A JULY 23, 2007 PRELIMINARY Units °C V ...

Page 5

... PRELIMINARY (2) Minimum Typical Maximum 345 245 3 (2) Minimum Typical Maximum ±5 ±5 -0.7 -1.2 -0.3 3.6 1.7 0 1.65 1.25 (2) Minimum Typical Maximum ±5 ±5 -0.7 -1.2 -0.3 3.6 0.1 0. the "true" input level and TR IDT5T9304 REV. A JULY 23, 2007 Units Units µA µ Units µA µ ...

Page 6

... A (2) (3) (4) (AC) specification under actual use conditions. DIF specification under actual use conditions (2) Minimum Typical 247 247 1.125 1 Value 1 750 50 Crossing Point 2 IDT5T9304 REV. A JULY 23, 2007 PRELIMINARY Maximum Units 454 mV 454 1.375 Units V/ns ...

Page 7

... X LVEPECL (2) LVPECL (3) (4) (AC) specification under actual use conditions. DIF X 7 Value 1 900 50 Crossing Point 2 = -40°C to 85°C A Maximum 1082 1880 Crossing Point specification under actual use conditions. IDT5T9304 REV. A JULY 23, 2007 PRELIMINARY Units V/ns Units 732 V/ns ...

Page 8

... A (3) – required for switching where / Maximum 400 1.2 50 Crossing Point 2 Minimum Typical Maximum 0.1 3 -0.3 3.6 is the “true” input level and V TR IDT5T9304 REV. A JULY 23, 2007 PRELIMINARY Units V/ns Units V/ns has DIF is the CP ...

Page 9

... Test Conditions (2) A Crosspoint to Qn/Qn Crosspoint , THI levels and temperature Minimum Typical Maximum 25 250 TBD 1.7 1.4 and tp of any differential output pair under identical HL LH IDT5T9304 REV. A JULY 23, 2007 PRELIMINARY Units 450 MHz 3.5 ns 3.5 ns 100 µS 100 µS ...

Page 10

... IIDT™ LVDS CLOCK BUFFER TERABUFFER™ PHL t SK(O) t PGD 10 PRELIMINARY + V DIF DIF - V DIF + V DIF DIF - V DIF + V DIF DIF - V DIF + V DIF V DIF - V DIF THI THI PGE + V DIF V DIF - V DIF IDT5T9304 REV. A JULY 23, 2007 = ...

Page 11

... Qn/Qn goes DIF IIDT™ LVDS CLOCK BUFFER TERABUFFER™ the Power Down Timing diagram this PRELIMINARY +V DIF V =0 DIF -V DIF +V DIF V =0 DIF -V DIF THI THI DIF V =0 DIF -V DIF IDT5T9304 REV. A JULY 23, 2007 ...

Page 12

... Table 6A. Differential Input Test Conditions Symbol V = 2.5V ± 0. Crossing of A and A THI IIDT™ LVDS CLOCK BUFFER TERABUFFER™ II ~50Ω Transmission Line ~50Ω Transmission Line Unit V 12 PRELIMINARY D.U. Scope 50Ω 50Ω IDT5T9304 REV. A JULY 23, 2007 ...

Page 13

... D.U. D.U. Unit pF pF Ω 50Ω 50Ω /E specification load is for reference only – 644 specifies 5pF between the output pair. IA IDT5T9304 REV. A JULY 23, 2007 PRELIMINARY SCOPE 50Ω 50Ω ...

Page 14

... Ordering Information Table 7. Ordering Information XX XXXXX IDT Package Device Type IIDT™ LVDS CLOCK BUFFER TERABUFFER™ Process I PG PGG 5T9304 14 PRELIMINARY - +85 C (Industrial) Thin Shrink Small Outline Package TSSOP - Green 2.5V LVDS 1:4 Glitchless Clock Buffer Terabuffer II IDT5T9304 REV. A JULY 23, 2007 ...

Page 15

... IDT5T9304 2.5V LVDS 1:4 CLOCK BUFFER TERABUFFER™ II Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...

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