IDT72V223 IDT [Integrated Device Technology], IDT72V223 Datasheet
IDT72V223
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IDT72V223 Summary of contents
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... OUTPUT REGISTER * Q -Q (x9 or x18 IDT72V223, IDT72V233 IDT72V243, IDT72V253 IDT72V263, IDT72V273 IDT72V283, IDT72V293 LD SEN OFFSET REGISTER FF/IR PAF EF/OR PAE FLAG HF LOGIC ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 DESCRIPTION: The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/ 72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/ x18 data flow. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 DESCRIPTION (CONTINUED) Each FIFO has a data input port (D ) and a data output port (Q n which can assume either an 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) during the Master Reset cycle ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 DESCRIPTION (CONTINUED) not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW- to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 PIN DESCRIPTION (TQFP & BGA PACKAGES) Symbol Name I/O BE During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will (1) *Big-Endian/ I Little-Endian select Little-Endian format. ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES) Symbol Name I/O RM (1) Retransmit Timing I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select Mode normal latency mode ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating (2) V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. 5. TQFP package only: for speed grades 7.5ns, 10ns and 15ns the minimum for t 6. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7.5ns speed grades. TM NARROW BUS FIFO ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.15V 0°C to +70°C;Industrial Symbol Parameter (4) f Cycle Frequency (Asynchronous mode) A (4) t Data Access Time AA t (4) Cycle Time CYC ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels ...
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... IDT72V263, 8,194th word for IDT72V273, 16,386th word for the IDT72V283 and 32,770th word for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, (D the 514th word for the IDT72V223, 1,026th word for IDT72V233, 2,050th word for the IDT72V243, 4,098th word ...
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... If no reads are performed after a reset, IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected 513 writes for the IDT72V223, 1,025 writes for the IDT72V233, 2,049 writes for the IDT72V243, 4,097 writes for the IDT72V253, 8,193 writes for the IDT72V263, 16,385 writes for the IDT72V273, 32,769 writes for the IDT72V283 and 65,537 writes for the IDT72V293 ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE IDT72V223 ≠ IDT72V223 IDT72V233 x18 Number of (n+1) to 256 (n+1) to 512 Words in (2) 257 to (512-(m+1)) ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 1st Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER 2nd Parallel Offset Write/Read Cycle ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K WEN REN SEN WCLK NOTES: 1. The programming method can only be selected at Master Reset. ...
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... IDT72V283 and 34 bits for the IDT72V293. For any other mode of operation (that includes x18 bus width on either the Input or Output), minus 2 bits from the values above. So, a total of 18 bits for the IDT72V223, 20 bits for the IDT72V233, 22 bits for the IDT72V243, 24 bits for the IDT72V253, 26 bits for the IDT72V263, 28 bits for the IDT72V273, 30 bits for the IDT72V283 and 32 bits for the IDT72V293 ...
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... IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293. In FWFT mode, if x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293 ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data ( data inputs for 9-bit wide data ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI) This is a dual purpose pin. During Master Reset, the state of the FWFT/ SI input determines whether the device will operate in IDT Standard mode or First Word Fall Through (FWFT) mode ...
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... When the FIFO is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the FIFO is not full reads are performed after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected 512 for the IDT72V223, TM NARROW BUS FIFO ...
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... In FWFT mode reads are performed after reset (MRS or PRS), HF will go LOW after (D-1 writes to the FIFO. If x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293 ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS ASYW, ASYR t RSS FSEL0, FSEL1 t RSS OW RSS BE t RSS RM t RSS PFM t RSS IP t RSS ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K WRITE WCLK 1 t (1) SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t 1 ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K NARROW BUS FIFO TM NARROW BUS FIFO 27 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K NARROW BUS FIFO COMMERCIAL AND INDUSTRIAL 28 TEMPERATURE RANGES ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293 ...
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... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293 ...
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... No more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293 ...
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... for the IDT72V283 and for the IDT72V293. 2. All other modes for the IDT72V223 for the IDT72V233 for the IDT72V243 for the IDT72V253 for the IDT72V263 for the IDT72V273 for the IDT72V283 and for the IDT72V293. ...
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... IDT72V293. In FWFT mode: if x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293 ...
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... IDT72V293. In FWFT mode: if x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293 ...
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... IDT72V283 and 131,072 for the IDT72V293 FWFT mode maximum FIFO depth. If x18 Input or x18 Output bus Width is selected 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293 ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 RCLK REN FFA NOTE LOW and WEN = LOW. Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode) 1 RCLK ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K Write WCLK 1 WEN SKEW t CYL Last Word W X NOTE LOW and REN = LOW. ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K CYC t t CYH CYL Last Word in O/P Register t RPE t EFA EF NOTES LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. ...
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... Figure 29 demonstrates a width expansion using two IDT72V223/72V233/ 72V243/72V253/72V263/72V273/72V283/72V293 devices. If x18 Input or x18 Output bus Width is selected, D input bus and Q x9 Input and x9 Output bus Widths are selected 18-bit wide input bus and Q bus. Any word width can be attained by adding additional IDT72V223/72V233/ 72V243/72V253/72V263/72V273/72V283/72V293 devices ...
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... IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. When both x9 Input and x9 Output bus Widths are selected, depths greater than 1,024 can be adapted for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293 ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K TCK TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol ...
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... JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V223/72V233/72V243/ 72V253/72V263/72V273/72V283/72V293 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K Test-Logic 0 Run-Test/ Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. ...
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... IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II 512 x 18 9/18 9/18 9/18 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9 THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used to select the test to be performed, or the test data register to be accessed, or both ...
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... Device Type Power Speed NOTE: 1. Industrial temperature range product for the 10ns is available as a standard device. All other speed grades are available by special order. 2. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7.5ns speed grades. DATASHEET DOCUMENT HISTORY 12/18/2000 pgs and 37. 03/27/2001 pgs ...