ISL45042A Intersil Corporation, ISL45042A Datasheet
ISL45042A
Related parts for ISL45042A
ISL45042A Summary of contents
Page 1
... The full-scale sink current of the ISL45042A is set using an external resister connected to the SET pin. The full-scale sink current determines the lowest voltage of the external voltage divider. The ISL45042A is available 3mmx3mm Thin DFN package with a maximum thickness of 0.8mm for ultra thin LCD panel design. Pinout ...
Page 2
... No Connect. Not internally connected. GND Ground connection. V ISL45042A power supply input. Bypass to GND with 0.1µF de-coupling capacitor. DD CTL Internal Counter Up/Down Control and Internal EEPROM Programming Control Input high, a mid-to-low transition increments the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at OUT ...
Page 3
... Operating Conditions Temperature Range ISL45042AIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
Page 4
... A Typical Current of 20µA is Calculated using the AVDD = 10V and RSET = 24.9kΩ. The maximum suggested SET Current should be 120µA. Application Information The application circuit to adjust the VCOM voltage in an LCD panel is shown in Figure 1. The ISL45042A has a 128-step sink current resolution. The output is connected to an external voltage divider, that results in decreasing the output VCOM voltage as you increase the ISL45042A sink current ...
Page 5
... FIGURE 4. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042A 5 ISL45042A To avoid unintentional adjustment, the ISL45042A guarantees to reject CTL pulses shorter than 20µs. During Initial Power-up (only), to avoid the possibility of a false pulse (since the internal comparators come unknown state) the very first CTL pulse is ignored ...
Page 6
... FIGURE 5. APPLICATION GENERATING VDD AND VCE equal to SET ISL45042A Truth Table The ISL45042A truth table is shown in Table 2. For proper operation the CE should be disabled (pulled low) before powering the device down to assure that the glitches and transients will not cause unwanted EEPROM overwriting. ...
Page 7
... THE VERY 1ST CTL PULSE IS IGNORED. VCOM THE TIMING DIAGRAM ABOVE SHOWS POST POWER-UP TIMING. 7 ISL45042A CTL MTC CTL ILMPW STOP PROGRAMMING IGNORES 1ST PULSE AFTER PROGRAMMING FIGURE 6. ISL45042A TIMMING DIAGRAM CTL IHRPW CTL ILRPW START PROGRAMMING 7A October 13, 2006 FN6158.2 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 ISL45042A L8.3x3A 2X 0.15 ...