MC74HC161 ONSEMI [ON Semiconductor], MC74HC161 Datasheet

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MC74HC161

Manufacturer Part Number
MC74HC161
Description
Presettable Counters
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

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MC74HC161A,
MC74HC163A
Presettable Counters
High–Performance Silicon–Gate CMOS
LS161 and LS163. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
with asynchronous and synchronous reset, respectively.
Î Î Î Î
Î Î Î Î
Î Î Î Î
Î Î Î Î
Î Î Î Î
Î Î Î Î
Î Î Î Î
March, 2000 – Rev. 8
ENABLES
COUNT
The MC74HC161A and HC163A are identical in pinout to the
The HC161A and HC163A are programmable 4–bit binary counters
No. 7A
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
Chip Complexity: 192 FETs or 48 Equivalent Gates
PRESET
Semiconductor Components Industries, LLC, 2000
INPUTS
DATA
HC161A
HC163A
Device
CLOCK
ENABLE P
Î Î Î Î
Î Î Î Î
Î Î Î Î
Î Î Î Î
Î Î Î Î
Î Î Î Î
Î Î Î Î
ENABLE T
P0
P1
P2
P3
RESET
LOAD
3
4
5
6
2
Count
Binary
Binary
Mode
10
1
9
7
Î Î Î Î Î Î
Î Î Î Î Î Î
Î Î Î Î Î Î
Î Î Î Î Î Î
Î Î Î Î Î Î
Î Î Î Î Î Î
Î Î Î Î Î Î
LOGIC DIAGRAM
Asynchronous
Synchronous
Reset Mode
PIN 16 = V CC
PIN 8 = GND
14
13
12
11
15
Q0
Q1
Q2
Q3
RIPPLE
CARRY
OUT
OUTPUT
BCD OR
BINARY
1
*HC163A only. HC161A is an Asynchronous Reset Device
H = high level, L = low level, X = don’t care
Clock
Reset*
H
H
H
H
L
ENABLE P
16
MC74HC16xAN
MC74HC16xAD
MC74HC16xADR2
16
CLOCK
RESET
Load
Inputs
GND
X
H
H
H
1
L
P0
P1
P2
P3
FUNCTION TABLE
1
PIN ASSIGNMENT
Device
ORDERING INFORMATION
Enable P
1
2
3
4
5
6
7
8
A
WL = Wafer Lot
YY = Year
WW = Work Week
X
X
H
X
L
http://onsemi.com
CASE 751B
= Assembly Location
CASE 648
N SUFFIX
D SUFFIX
PDIP–16
SO–16
16
15
14
13
12
10
11
Enable T
9
Publication Order Number:
X
X
H
X
L
SOIC–16
SOIC–16
Package
PDIP–16
V CC
RIPPLE
CARRY OUT
Q0
Q1
Q2
Q3
ENABLE T
LOAD
Load Preset Data
16
16
1
1
MC74HC16xAN
MC74HC161A/D
DIAGRAMS
MARKING
AWLYYWW
No Count
No Count
AWLYWW
Output
HC16xA
Reset
Count
2500 / Reel
2000 / Box
Shipping
48 / Rail
Q

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MC74HC161 Summary of contents

Page 1

... MC74HC161A, MC74HC163A Presettable Counters High–Performance Silicon–Gate CMOS The MC74HC161A and HC163A are identical in pinout to the LS161 and LS163. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC161A and HC163A are programmable 4–bit binary counters with asynchronous and synchronous reset, respectively ...

Page 2

... MC74HC161A, MC74HC163A Î Î Î Î Î Î Î Î ...

Page 3

... NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). MC74HC161A, MC74HC163A (Voltages Referenced to GND) Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... Power Dissipation Capacitance (Per Gate)* * Used to determine the no–load dynamic power consumption For load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). MC74HC161A, MC74HC163A ( pF, Input 6.0 ns) Î Î Î ...

Page 5

... MC74HC161A, MC74HC163A Î Î Î Î Î Î Î ...

Page 6

... Q3 low MC74HC161A, MC74HC163A FUNCTION DESCRIPTION level. The HC161A resets asynchronously, and the HC163A resets with the rising edge of the Clock input (synchronous reset). Loading With the rising edge of the Clock, a low level on Load (Pin 9) loads the data from the Preset Data input pins (P0, P1, P2, P3) into the internal flip– ...

Page 7

... CARRY 10% OUT t TLH Figure 3. VALID INPUTS P0, P1, 50% P2 50% LOAD rec CLOCK 50% Figure 5. MC74HC161A, MC74HC163A SWITCHING WAVEFORMS V CC RESET GND t PHL ANY OUTPUT CLOCK RESET GND PHL CLOCK t THL V CC GND V CC ENABLE T OR ...

Page 8

ENABLE P 10 ENABLE T 1 RESET 9 LOAD 2 CLOCK LOAD Q0 LOAD LOAD Q1 LOAD ...

Page 9

... MC74HC161A, MC74HC163A Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one and two. 4. Inhibit. RESET (HC161A) (ASYNCHRONOUS) RESET (HC163A) (SYNCHRONOUS) LOAD P0 PRESET P1 DATA INPUTS P2 P3 CLOCK (HC161A) CLOCK (HC163A) ENABLE P COUNT ENABLES ENABLE OUTPUTS ...

Page 10

ENABLE P 10 ENABLE T 1 RESET 9 LOAD 2 CLOCK LOAD Q0 LOAD LOAD Q1 LOAD ...

Page 11

... LOAD ENABLE P ENABLE T LOAD ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK CLOCK RESET OUTPUTS MC74HC161A, MC74HC163A INPUTS LOAD ENABLE P RIPPLE CARRY ENABLE T OUT CLOCK OUTPUTS Figure 11. N–Bit Synchronous Counters INPUTS LOAD ...

Page 12

... OPTIONAL BUFFER INPUTS FOR NOISE REJECTION RESET Figure 13. Modulo–5 Counter The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch–free due to the synchronous Reset. MC74HC161A, MC74HC163A HC163A OTHER Q0 INPUTS Q1 OUTPUT Q2 Q3 RESET Figure 14. Modulo–11 Counter http://onsemi ...

Page 13

... MC74HC161A, MC74HC163A –A – –T – 0.25 (0.010 –A – –B – –T – SEATING PLANE 0.25 (0.010 PACKAGE DIMENSIONS PDIP–16 N SUFFIX CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI 2 ...

Page 14

... Notes MC74HC161A, MC74HC163A http://onsemi.com 14 ...

Page 15

... Notes MC74HC161A, MC74HC163A http://onsemi.com 15 ...

Page 16

... English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland MC74HC161A, MC74HC163A CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – ...

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