MC74HC74 ONSEMI [ON Semiconductor], MC74HC74 Datasheet

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MC74HC74

Manufacturer Part Number
MC74HC74
Description
Dual D Flip-Flop with Set and Reset
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

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MC74HC74A
Dual D Flip-Flop with Set
and Reset
High–Performance Silicon–Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
and Clock inputs. Information at a D–input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip–flop. The Set
and Reset inputs are asynchronous.
*Both outputs will remain high as long as Set and Reset are low, but the output
March, 2000 – Rev. 8
states are unpredictable if Set and Reset go high simultaneously.
The MC74HC74A is identical in pinout to the LS74. The device
This device consists of two D flip–flops with individual Set, Reset,
No. 7A
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
Chip Complexity: 128 FETs or 32 Equivalent Gates
Semiconductor Components Industries, LLC, 2000
RESET 1
CLOCK 1
CLOCK 2
RESET 2
DATA 1
Set Reset Clock Data
DATA 2
H
H
H
H
H
H
L
L
SET 1
SET 2
H
H
H
H
H
H
L
L
FUNCTION TABLE
Inputs
LOGIC DIAGRAM
13
12
11
10
1
2
3
4
X
X
X
H
L
X
X
X
H
X
X
X
L
5
6
9
8
No Change
No Change
No Change
H*
Outputs
Q
H
H
L
L
Q1
Q2
Q2
Q1
H*
Q
H
H
L
L
PIN 14 = V CC
PIN 7 = GND
1
MC74HC74AN
MC74HC74AD
MC74HC74ADR2
MC74HC74ADT
MC74HC74ADTR2
Device
CLOCK 1
RESET 1
ORDERING INFORMATION
DATA 1
A
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
SET 1
GND
PIN ASSIGNMENT
http://onsemi.com
Q1
Q1
CASE 751A
CASE 646
N SUFFIX
D SUFFIX
CASE 948G
SOIC–14
DT SUFFIX
PDIP–14
TSSOP–14
1
2
3
4
5
6
7
= Assembly Location
TSSOP–14
TSSOP–14
SOIC–14
SOIC–14
Publication Order Number:
Package
PDIP–14
14
13
12
11
10
9
8
14
14
1
1
MC74HC74AN
V CC
RESET 2
DATA 2
CLOCK 2
SET 2
Q2
Q2
DIAGRAMS
MC74HC74A/D
MARKING
AWLYYWW
AWLYWW
14
1
HC74A
2500 / Reel
2500 / Reel
2000 / Box
Shipping
55 / Rail
96 / Rail
ALYW
74A
HC

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MC74HC74 Summary of contents

Page 1

... Dual D Flip-Flop with Set and Reset High–Performance Silicon–Gate CMOS The MC74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip–flops with individual Set, Reset, and Clock inputs. Information at a D– ...

Page 2

... MC74HC74A Î Î Î Î Î Î Î Î Value Unit Î ...

Page 3

... Power Dissipation Capacitance (Per Flip–Flop)* * Used to determine the no–load dynamic power consumption For load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D). MC74HC74A (Voltages Referenced to GND) Î Î Î Î Î Î Î Î Î ...

Page 4

... MC74HC74A Î Î Î Î Î Î Î Î ...

Page 5

... TLH t THL Figure 1. VALID 50% DATA 50% CLOCK Figure SET 2, 12 DATA 1, 13 RESET MC74HC74A SWITCHING WAVEFORMS 50% SET OR RESET GND 50 50 CLOCK V CC GND DEVICE UNDER V CC TEST GND *Includes all probe and jig capacitance ...

Page 6

... D –A– –B– –T– SEATING 14 PL PLANE 0.25 (0.010 MC74HC74A PACKAGE DIMENSIONS PDIP–14 N SUFFIX CASE 646–06 ISSUE SOIC–14 D SUFFIX CASE 751A–03 ISSUE 0.25 (0.010 ...

Page 7

... L PIN 1 IDENT 0.15 (0.006 –V– C 0.10 (0.004) –T– SEATING G D PLANE MC74HC74A PACKAGE DIMENSIONS TSSOP–14 DT SUFFIX CASE 948G–01 ISSUE 0.25 (0.010 –U– F DETAIL Ç Ç É É ...

Page 8

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5740–2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC74HC74A/D ...

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