MT48LC8M8A2-8E Micron Semiconductor Products, MT48LC8M8A2-8E Datasheet
MT48LC8M8A2-8E
Manufacturer Part Number
MT48LC8M8A2-8E
Description
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT48LC8M8A2-8E.pdf
(55 pages)
Specifications of MT48LC8M8A2-8E
Date_code
09+
SYNCHRONOUS
DRAM
FEATURES
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on
• Internal pipelined operation; column address can
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
• Configurations
• WRITE Recovery (
• Plastic Package – OCPL
• Timing (Cycle Time)
• Self Refresh
• Operating Temperature Range
NOTE: 1. Refer to Micron Technical Note: TN-48-05.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
positive edge of system clock
be changed every clock cycle
PRECHARGE, and Auto Refresh Modes
t
54-pin TSOP II (400 mil)
10ns @ CL = 2 (PC100)
7.5ns @ CL = 3 (PC133)
7.5ns @ CL = 2 (PC133)
6ns @ CL = 3 (PC133, x16 Only)
Standard
Low Power
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
WR = “2 CLK”
16 Meg x 4
8 Meg x 8
4 Meg x 16 (1 Meg x 16 x 4 banks)
2. Off-center parting line.
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatibility.
MT48LC8M8A2TG-75
1
(4 Meg x 4
(2 Meg x 8
Part Number Example:
t
WR)
2
x 4 banks)
x 4 banks)
MARKING
16M4
None
None
4M16
8M8
-8E
-75
-7E
-6
IT
TG
A2
L
3
3, 4,5
1
MT48LC16M4A2 – 4 Meg x 4 x 4 banks
MT48LC8M8A2 –
MT48LC4M16A2 – 1 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
KEY TIMING PARAMETERS
* CL = CAS (READ) latency
GRADE
-8E
-8E
Note: The # symbol indicates signal is active LOW. A dash (–)
SPEED
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
DQ0
DQ1
x4
-7E
-75
-7E
-75
NC
NC
NC
NC
NC
NC
NC
-6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3, 4, 5
3, 4, 5
www.micron.com/dramds
DQ0
DQ1
DQ2
DQ3
x8
NC
NC
NC
NC
NC
PIN ASSIGNMENT (Top View)
indicates x8 and x4 pin function is same as x16 pin function.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DQML
FREQUENCY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
V
V
x16
CAS#
RAS#
VssQ
VssQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
WE#
DD
DD
BA0
BA1
A10
V
V
V
CS#
A0
A1
A2
A3
166 MHz
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
DD
DD
DD
CLOCK
Q
Q
4 Meg x 4 x 4 banks
16 Meg x 4
4 (BA0, BA1)
4K (A0-A11)
1K (A0-A9)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54-Pin TSOP
2 Meg x 8 x 4 banks
4K
CL = 2* CL = 3*
64Mb: x4, x8, x16
ACCESS TIME
5.4ns
6ns
6ns
–
–
–
–
2 Meg x 8 x 4 banks
4 (BA0, BA1)
4K (A0-A11)
512 (A0-A8)
8 Meg x 8
5.5ns
5.4ns
5.4ns
4K
6ns
–
–
–
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
©2003, Micron Technology, Inc.
SETUP
TIME
x16
Vss
DQ15
VssQ
DQ14
DQ13
V
DQ12
DQ11
VssQ
DQ10
DQ9
V
DQ8
Vss
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
1.5ns
1.5ns
1.5ns
1.5ns
1.5ns
SDRAM
2ns
2ns
DD
DD
1 Meg x 16 x 4 banks
Q
Q
4 Meg x 16
4 (BA0, BA1)
4K (A0-A11)
256 (A0-A7)
x8
-
DQ7
-
NC
DQ6
-
NC
DQ5
-
NC
DQ4
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
4K
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
1ns
1ns
1ns
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
x4
-