nb100lvep91 ON Semiconductor, nb100lvep91 Datasheet

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nb100lvep91

Manufacturer Part Number
nb100lvep91
Description
2.5v / 3.3v Any Level Positive Input To -2.5v -3.3v / -5v Necl Output Translator
Manufacturer
ON Semiconductor
Datasheet

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NB100LVEP91
2.5 V/3.3 V Any Level
Positive Input to
-2.5 V/-3.3 V LVNECL
Output Translator
Description
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
LVNECL output signals (−2.5 V / −3.3 V).
power rails. The V
supply, and the V
supply. The GND pins are connected to the system ground plane. Both
V
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
this device only. For single-ended input conditions, the unused
differential input is connected to V
V
and V
to 0.5 mA. When not used, V
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 18
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
EE
BB
The NB100LVEP91 is a triple any level positive input to NECL
To accomplish the level translation the LVEP91 requires three
Under open input conditions, the D input will be biased at V
The V
V
Maximum Input Clock Frequency > 2.0 GHz Typical
Maximum Input Data Rate > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range: V
Q Output will Default LOW with Inputs Open or at GND
Pb−Free Packages are Available*
EE
and V
may also rebias AC coupled inputs. When used, decouple V
CC
= −2.375 V to −3.8 V; GND = 0 V
BB
via a 0.01 mF capacitor and limit current sourcing or sinking
CC
pin, an internally generated voltage supply, is available to
should be bypassed to ground via 0.01 mF capacitors.
EE
CC
pin should be connected to the negative power
pins should be connected to the positive power
CC
= 2.375 V to 3.8 V;
BB
should be left open.
BB
as a switching reference voltage.
1
CC
BB
/2
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
20
*For additional marking information, refer to
DW SUFFIX
CASE 751D
SO−20 WB
(Note: Microdot may be in either location)
Application Note AND8002/D.
24 PIN QFN
MN SUFFIX
CASE 485L
24
ORDERING INFORMATION
1
A
WL, L
YY, Y
WW, W = Work Week
G or G
1
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
20
MARKING DIAGRAMS*
1
Publication Order Number:
NB100LVEP91
1
AWLYYWWG
24
NB100LVEP91/D
ALYWG
VP91
N100
G

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nb100lvep91 Summary of contents

Page 1

... Positive Input to -2.5 V/-3.3 V LVNECL Output Translator Description The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential LVNECL output signals (−2 −3.3 V). To accomplish the level translation the LVEP91 requires three power rails ...

Page 2

Positive Level Table 1. PIN DESCRIPTION Pin SOIC QFN Name 15 14, 17 19, 20, 23, GND ...

Page 3

... Machine Model Charged Device Model SO−20 WB QFN−24 Oxygen Index http://onsemi.com 3 Exposed Pad (EP GND GND NB100LVEP91 (not GND). Value > > 150 V > ...

Page 4

Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply CC V Negative Power Supply EE V Positive Input Voltage I V Operating Voltage OP I Output Current out I PECL V Sink/Source Operating Temperature Range A ...

Page 5

Table 5. DC CHARACTERISTICS POSITIVE INPUT Symbol Characteristic I Positive Power Supply Current CC V Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended PECL Output Voltage Reference BB V Input HIGH Voltage Common Mode Range IHCMR ...

Page 6

Table 7. AC CHARACTERISTICS V Symbol Characteristic V Output Voltage Amplitude OUTPP (Figure 4) (Note 9) t Propagation Delay PLH PHL0 t Pulse Skew (Note 10) SKEW Output−to−Output (Note 11) Part−to−Part (Diff) (Note 11) t RMS ...

Page 7

... Application Information All NB100LVEP91 inputs can accept LVPECL, LVTTL, LVCMOS, HSTL, CML, or LVDS signal levels. The limitations for differential input signal (LVDS, HSTL, LVPECL, or CML) are the minimum input swing of 150 LVPECL Driver GND − 2 Figure 6 ...

Page 8

... ORDERING INFORMATION Device NB100LVEP91DW NB100LVEP91DWG NB100LVEP91DWR2 NB100LVEP91DWR2G NB100LVEP91MN NB100LVEP91MNG NB100LVEP91MNR2 NB100LVEP91MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Q Driver Device Q Figure 12. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − ...

Page 9

20X 0. 18X A1 T PACKAGE DIMENSIONS SO−20 WB CASE 751D−05 ISSUE G q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS ...

Page 10

... FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A2 0.60 0.80 A3 0.20 REF b 0.23 0.28 D 4.00 BSC D2 2.70 2.90 E 4.00 BSC E2 2.70 2.90 e 0.50 BSC L 0.35 0.45 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB100LVEP91/D ...

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