NB7L111MMN ON Semiconductor, NB7L111MMN Datasheet
NB7L111MMN
Specifications of NB7L111MMN
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NB7L111MMN Summary of contents
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... W Internal Input and Output Termination Resistors • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev ...
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Exposed Pad (EP VTCLK0 2 3 CLK0 CLK0 4 VTCLK0 5 VTSEL 6 7 SEL SEL 8 VTSEL 9 VTCLK1 10 11 CLK1 CLK1 12 VTCLK1 13 Figure 1. Pinout (Top View VTCLK0 ...
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Table 2. PIN DESCRIPTION Pin Name 15, 24, 27, 39, 42 18, 21, 26, 30, 33 36, 40, 45 VTCLK0 3 CLK0 4 CLK0 5 VTCLK0 6 VTSEL 7 SEL 8 SEL ...
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Table 3. ATTRIBUTES Input Default State Resistors ESD Protection Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS (Note 4) ...
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Table 5. DC CHARACTERISTICS V Symbol Characteristic I Power Supply Current (Inputs and Outputs Open Output HIGH Voltage (Notes 6 and Output LOW Voltage (Notes 6 and 7) OL DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (See Figures ...
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Table 6. AC CHARACTERISTICS V Symbol Characteristic V Output Voltage Amplitude (@ V OUTPP (See Figures and 2.375 V to 2.625 3.135 V to 3.465 Maximum Operating ...
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INPUT CLOCK FREQUENCY (GHz) Figure 3. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (V = 400 mV; V inpp CC 400 350 ...
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Device DDJ = 6 ps TIME (22.1 ps/div) Figure 8. Typical Output Waveform at 3.125 Gb/s with PRBS 2 Device DDJ=16ps TIME (22.1 ps/div) Figure 9. Typical Output Waveform at 5 Gb/s with PRBS 2 Device DDJ=12ps TIME (22.1 ps/div) ...
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CLK CLK Q Q NB7L111M Figure 12. Typical Termination for 16 mA Output Drive and Device Evaluation CLK V th CLK V th Figure 13. Differential Input Driven Single−Ended thmax IHmax V ILmax ...
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Table 7. Interfacing Options INTERFACING OPTIONS CML Connect VTCLK0, VTCLK0, VTCLK1, VTCLK1, VTSEL, VTSEL to V LVDS Connect VTCLK0, VTCLK0 together for CLK0 input; Connect VTCLK1, VTCLK1 together for CLK1 input; Connect VTSEL, VTSEL together for SEL control input. AC−COUPLED ...
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Application Information All NB7L111M inputs can accept LVPECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing and the maximum input CML ...
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... LVCMOS Driver V EE Figure 21. LVCMOS/LVTTL to CML Receiver Interface ORDERING INFORMATION Device NB7L111MMN NB7L111MMNG NB7L111MMNR2 NB7L111MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ Connect No Connect V REF Package QFN− ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...