PIC24F08KA101-I/SO Microchip Technology, PIC24F08KA101-I/SO Datasheet - Page 133
PIC24F08KA101-I/SO
Manufacturer Part Number
PIC24F08KA101-I/SO
Description
IC PIC MCU FLASH 8K 20-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA240017.pdf
(254 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F16KA101-ISS.pdf
(18 pages)
Specifications of PIC24F08KA101-I/SO
Core Size
16-Bit
Program Memory Size
8KB (2.75K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Controller Family/series
PIC24
No. Of I/o's
18
Eeprom Memory Size
512Byte
Ram Memory Size
1.5KB
Cpu Speed
32MHz
No. Of Timers
3
Core
PIC
Processor Series
PIC24F
Data Bus Width
16 bit
Maximum Clock Frequency
32 KHz
Data Ram Size
1.5 KB
On-chip Adc
10 bit, 9 Channel
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Mounting Style
SMD/SMT
Height
2.05 mm
Interface Type
I2C, IrDA, SPI, UART
Length
12.8 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Width
7.5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / Rohs Status
Details
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REGISTER 16-1:
© 2009 Microchip Technology Inc.
bit 1
bit 0
SPITBF: SPI1 Transmit Buffer Full Status bit
1 = Transmit not yet started, SPI1TXB is full
0 = Transmit started, SPI1TXB is empty
In Standard Buffer mode:
Automatically set in hardware when CPU writes SPI1BUF location, loading SPI1TXB.
Automatically cleared in hardware when SPI1 module transfers data from SPI1TXB to SPI1SR.
In Enhanced Buffer mode:
Automatically set in hardware when CPU writes SPI1BUF location, loading the last available buffer location.
Automatically cleared in hardware when a buffer location is available for a CPU write.
SPIRBF: SPI1 Receive Buffer Full Status bit
1 = Receive complete, SPI1RXB is full
0 = Receive is not complete, SPI1RXB is empty
In Standard Buffer mode:
Automatically set in hardware when SPI1 transfers data from SPI1SR to SPI1RXB.
Automatically cleared in hardware when core reads SPI1BUF location, reading SPI1RXB.
In Enhanced Buffer mode:
Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread
buffer location.
Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR.
SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED)
Preliminary
PIC24F16KA102 FAMILY
DS39927B-page 131
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