PIC18F26K20-E/SP Microchip Technology, PIC18F26K20-E/SP Datasheet - Page 322
![IC PIC MCU FLASH 32KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F26K20-E/SP
Manufacturer Part Number
PIC18F26K20-E/SP
Description
IC PIC MCU FLASH 32KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F26K20-E/SP
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 322 of 430
- Download datasheet (7Mb)
PIC18F2XK20/4XK20
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41303D-page 320
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG =
FLAG_REG =
Q1
register ‘f’
Bit Clear f
BCF
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
0 → f<b>
None
Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
BCF
Read
1001
Q2
f, b {,a}
C7h
47h
FLAG_REG,
bbba
Process
Data
Q3
ffff
7, 0
register ‘f’
Write
Q4
ffff
Preliminary
BN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If NEGATIVE =
If NEGATIVE =
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Negative
BN
-128 ≤ n ≤ 127
if NEGATIVE bit is ‘1’
(PC) + 2 + 2n → PC
None
If the NEGATIVE bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
© 2008 Microchip Technology Inc.
n
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
0110
BN
operation
Process
Process
Data
Data
Q3
No
Q3
Jump
nnnn
Write to PC
operation
operation
Q4
No
Q4
No
nnnn
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