PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet

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PIC18F27J53-I/SP

Manufacturer Part Number
PIC18F27J53-I/SP
Description
IC PIC MCU 128KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
DIP
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F27J53-I/SP
Manufacturer:
MITSUBISHI
Quantity:
12
1.0
This document includes the programming specifications
for the following devices:
• PIC18F24J10
• PIC18F25J10
• PIC18F44J10
• PIC18F45J10
• PIC18F24J11
• PIC18F25J11
• PIC18F26J11
• PIC18F44J11
• PIC18F45J11
• PIC18F46J11
• PIC18F26J13
• PIC18F27J13
• PIC18F46J13
• PIC18F47J13
• PIC18F24J50
• PIC18F25J50
• PIC18F26J50
• PIC18F44J50
• PIC18F45J50
• PIC18F46J50
• PIC18F26J53
• PIC18F27J53
• PIC18F46J53
• PIC18F47J53
TABLE 2-1:
© 2009 Microchip Technology Inc.
MCLR
V
V
V
RB6
RB7
Legend: I = Input, O = Output, P = Power
Note 1:
DD
SS
DDCORE
Pin Name
and AV
and AV
DEVICE OVERVIEW
/V
Flash Microcontroller Programming Specification
All power supply and ground pins must be connected, including analog supplies (AV
(AV
CAP
SS (1)
DD (1)
SS
).
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XJXX/4XJXX FAMILY
Pin Name
V
MCLR
DDCORE
V
PGC
PGD
V
V
CAP
DD
SS
• PIC18LF24J10
• PIC18LF25J10
• PIC18LF44J10
• PIC18LF45J10
• PIC18LF24J11
• PIC18LF25J11
• PIC18LF26J11
• PIC18LF44J11
• PIC18LF45J11
• PIC18LF46J11
• PIC18LF26J13
• PIC18LF27J13
• PIC18LF46J13
• PIC18LF47J13
• PIC18LF24J50
• PIC18LF25J50
• PIC18LF26J50
• PIC18LF44J50
• PIC18LF45J50
• PIC18LF46J50
• PIC18LF26J53
• PIC18LF27J53
• PIC18LF46J53
• PIC18LF47J53
PIC18F2XJXX/4XJXX FAMILY
Pin Type
I/O
P
P
P
P
I
I
Programming Enable
Power Supply
Ground
Regulated Power Supply for Microcontroller Core
Filter Capacitor for On-Chip Voltage Regulator
Serial Clock
Serial Data
During Programming
2.0
The
programmed using In-Circuit Serial Programming™
(ICSP™). This programming specification applies to
devices of the PIC18F2XJXX/4XJXX family in all
package types.
2.1
The pin diagrams for the PIC18F2XJXX/4XJXX family
are shown in Figure 2-1 and Figure 2-2. The pins that
are required for programming are listed in Table 2-1
and shown in darker lettering in the diagrams.
PIC18F2XJXX/4XJXX
PROGRAMMING OVERVIEW
OF THE PIC18F2XJXX/4XJXX
FAMILY
Pin Diagrams
Pin Description
family
DD
) and ground
DS39687E-page 1
devices
are

PIC18F27J53-I/SP Summary of contents

Page 1

... PIC18LF26J50 • PIC18F44J50 • PIC18LF44J50 • PIC18F45J50 • PIC18LF45J50 • PIC18F46J50 • PIC18LF46J50 • PIC18F26J53 • PIC18LF26J53 • PIC18F27J53 • PIC18LF27J53 • PIC18F46J53 • PIC18LF46J53 • PIC18F47J53 • PIC18LF47J53 TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XJXX/4XJXX FAMILY Pin Name Pin Name ...

Page 2

... CAP RA5 OSC1 OSC2 10 11 RC0 18 RC1 12 17 RC2 13 16 RC3 RA2 21 RA3 2 20 PIC18F2XJ1X / CAP RA5 4 PIC18F2XJ5X RB7/PGD RB6/PGC RB5 RB4 RB3 RB2 RB1 RB0 RC7 RC6 RC5 RC4 RB3 RB2 RB1 RB0 RC7 © 2009 Microchip Technology Inc. ...

Page 3

... PDIP MCLR V DDCORE 44-Pin QFN 44-Pin TQFP 1 RC7 RD4 2 RD5 3 4 RD6 PIC18F4XJ1X RD7 PIC18F4XJ5X RB0 8 9 RB1 RB2 10 11 RB3 © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY 1 40 RA0 2 39 RA1 3 38 RA2 4 37 RA3 CAP 7 RA5 RE0 RE1 RE2 ...

Page 4

... PIC18F46J13 PIC18F26J50 PIC18F46J50 PIC18F26J53 PIC18F46J53 PIC18F27J13 PIC18F47J13 PIC18F27J53 PIC18F47J53 * Includes PIC18F and PIC18LF devices. For purposes of code protection, the program memory for every device is treated as a single block. Enabling code protection, thus protects the entire code memory, and not individual segments. ...

Page 5

... Section 5.1 “Device ID Word”. These device ID bits read out normally, even after code protection. © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY 2.2.1 MEMORY ADDRESS POINTER Memory in the device address space (000000h to ...

Page 6

... Read as ‘0’ Flash Conf. Words Unimplemented Read as ‘0’ Configuration Configuration Space Space Configuration Configuration Words Words Configuration Configuration Space Space Device IDs Device IDs © 2009 Microchip Technology Inc. (1) 000000h 003FFFh 007FFFh 00FFFFh 01FFFFh 1FFFFFh 200000h 2FFFFFh 300000h (2) 300007h 3FFFFEh 3FFFFFh ...

Page 7

... P13 P1 MCLR V DD PGD PGC P19 © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY 2.4 Entering and Exiting ICSP™ Program/Verify Mode Entry into ICSP modes for PIC18F2XJXX/4XJXX family devices is somewhat different than previous PIC18 devices. As shown in Figure 2-6, entering ICSP Program/Verify mode requires three steps: 1 ...

Page 8

... Data Payload PGD = Input COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload 3C 40 Table Write, post-increment P5A Fetch Next 4-Bit Command © 2009 Microchip Technology Inc. ...

Page 9

... FIGURE 3-2: BULK ERASE TIMING PGC P5 PGD 4-Bit Command 16-Bit Data Payload © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY TABLE 3-1: 4-Bit Command 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 1100 0000 0000 FIGURE 3-1: 1 ...

Page 10

... TBLPTRU CLRF TBLPTRH CLRF TBLPTRL BSF EECON1, FREE BSF EECON1, WR NOP – hold PGC high for time P10 P5A 4-Bit Command 16-Bit Data Payload PGD = Input family device. The timing P10 16-Bit Row-Erase Time Data Payload © 2009 Microchip Technology Inc. ...

Page 11

... FIGURE 3-4: SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 1024 © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Start Addr = 0 Configure Device for Row Erase Start Erase Sequence and Hold PGC High for Time P10 All No Rows Done? Yes Done DS39687E-page 11 ...

Page 12

... EECON1, WREN MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9. sequence to program necessary to completely write © 2009 Microchip Technology Inc ...

Page 13

... TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 PGC P5 PGD 4-Bit Command © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No Bytes Written? Yes Start Write Sequence and Hold PGC High Until Done ...

Page 14

... MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Repeat write operation 30 more times to fill the write buffer Write 2 bytes and start programming. NOP - hold PGC high for time P9. BCF EECON1, WREN © 2009 Microchip Technology Inc. ...

Page 15

... Before attempting to modify the contents of a specific byte of Flash memory a second time, an erase operation (either a Bulk Erase or a Row Erase which includes that byte) should be performed. © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY DS39687E-page 15 ...

Page 16

... Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out PGD = Output P5A MSb Fetch Next 4-Bit Command PGD = Input © 2009 Microchip Technology Inc. ...

Page 17

... Yes All No Code Memory Verified? Yes Done © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY 4.3 Blank Check The term “Blank Check” means to verify that the device has no programmed memory cells. All memories must be verified: code memory and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored ...

Page 18

... XFFAh 300002h XFFBh 300003h XFFCh 300004h XFFDh 300005h XFFEh 300006h XFFFh 300007h Default/ Bit 1 Bit 0 Unprogrammed Value — WDTEN 111- ---1 — — ---- 01-- FOSC1 FOSC0 11-- -111 ---- 1111 — CCP2MX ---- ---1 REV1 REV0 See Table DEV4 DEV3 See Table © 2009 Microchip Technology Inc. ...

Page 19

... CCP2MX CONFIG3H CCP2 MUX bit 1 = CCP2 is multiplexed with RC1 0 = CCP2 is multiplexed with RB3 © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Description purpose I/O pins (Legacy mode) OSCCON<1:0> DS39687E-page 19 ...

Page 20

... PLLDIV0 WDTEN 111- 1111 (3) (3) CPDIV1 CPDIV0 ---- 0111 FOSC1 FOSC0 11-1 1111 WDTPS1 WDTPS0 ---- 1111 RTCOSC DSWDTOSC 1111 1111 — IOL1WAY ---- 1--1 WPFP1 WPFP0 1111 1111 — WPDIS ---- ---1 REV1 REV0 xxxx xxxx DEV4 DEV3 0100 00xx © 2009 Microchip Technology Inc. ...

Page 21

... These bits are not implemented in PIC18F46J11 family devices. 4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code protection, perform an ICSP™ Bulk Erase operation. © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Description ...

Page 22

... Configuration Words page is erase/write-protected, regardless of WPEND and WPFP<5:0> settings Write/Erase Protect Region Select bit (valid when WPDIS = Flash pages, WPFP<5:0> to Configuration Words page, are write/erase-protected 0 = Flash pages WPFP<5:0> are write/erase-protected Reset reloaded with the programmed value at any device Reset. DD © 2009 Microchip Technology Inc. ...

Page 23

... These bits are not implemented in PIC18F47J13 family devices. 4: This bit should always be maintained at ‘0’. © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Description Write/Erase Protect Page Start/End Location bits Used with WPEND bit to define which pages in Flash will be write/erase-protected. ...

Page 24

... CLKO output signal active on the RA6 pin (EC mode only CLKO output disabled Secondary Oscillator Circuit Selection bits 11 = High-power SOSC circuit selected 10 = Digital Input mode (SCLKI Low-power SOSC circuit selected 00 = Reserved Reset reloaded with the programmed value at any device Reset. DD © 2009 Microchip Technology Inc. ...

Page 25

... Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code protection, perform an ICSP™ Bulk Erase operation. 5: Not implemented on PIC18F47J53 family devices. © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Description Oscillator Selection bits ...

Page 26

... Used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number. Revision ID bits Indicate the device revision. Device ID bits Used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. Reset reloaded with the programmed value at any device Reset. DD © 2009 Microchip Technology Inc. ...

Page 27

... PIC18LF44J11 PIC18LF45J11 PIC18LF46J11 PIC18F26J13 PIC18F27J13 PIC18F46J13 PIC18F47J13 PIC18LF26J13 PIC18LF27J13 PIC18LF46J13 PIC18LF47J13 PIC18F26J53 PIC18F27J53 DEVID1 PIC18F46J53 PIC18F47J53 PIC18LF26J53 PIC18LF27J53 PIC18LF46J53 PIC18LF47J53 5.2 Checksum Computation The checksum is calculated by summing the contents of all code memory locations and the device Configuration Words, appropriately masked. The Least Significant 16 bits of this sum are the checksum ...

Page 28

... On 0000h SUM[000000:01FFF7] + ([01FFF8] & FFh) + ([01FFF9] & FFh) + ([01FFFA] & FFh) + Off ([01FFFB] & FFh) + ([01FFFC] & FFh) + ([01FFFD] & FBh) + ([01FFFE] & FFh) + PIC18F27J53 ([01FFFF] & FBh) PIC18F47J53 On 0000h Legend: [a] = Value at address a; SUM[a:b] = Sum of locations inclusive Addition; & = Bitwise AND. ...

Page 29

... External power must be supplied to the V Section 2.1.1 “PIC18F2XJXX/4XJXX/ LF2XJXX/LF4XJXX Devices and the On-Chip Voltage Regulator” for more information must also be supplied to the and V , respectively © 2009 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Min Max 2.25 2.75 PIC18LFXXJXX V 3.60 DDCORE PIC18FXXJ10 2.70 3.60 PIC18FXXJ50 2 ...

Page 30

... See DDCORE CAP pins during programming. AV and Conditions μ PIC18F2XJ10/PIC18F4XJ10 ms PIC18F2XJ11/PIC18F4XJ11/ PIC18F2XJ13/PIC18F4XJ13/ PIC18F2XJ5X/PIC18F4XJ5X ms PIC18F2XJ10/PIC18F4XJ10/ PIC18F2XJ13/PIC18F4XJ13/ PIC18F2XJ53/PIC18F4XJ53 ms PIC18F2XJ11/PIC18F4XJ11/ PIC18F2XJ50/PIC18F4XJ50 ms PIC18F2XJ10/PIC18F4XJ10/ PIC18F2XJ13/PIC18F4XJ13/ PIC18F2XJ53/PIC18F4XJ53 ms PIC18F2XJ11/PIC18F4XJ11/ PIC18F2XJ50/PIC18F4XJ50 μ μ should always be within ±0.3V SS © 2009 Microchip Technology Inc. ...

Page 31

... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 32

... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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