T89C51CC02CA-TDSIM Atmel, T89C51CC02CA-TDSIM Datasheet - Page 104

• Manufacturer Part Number: T89C51CC02CA-TDSIM
• Description: IC 8051 MCU FLASH 16K 24SOIC
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of T89C51CC02CA-TDSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-SOIC (7.5mm Width)
• For Use With: AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: T89C51CC02CATDSIM

104
AT/T89C51CC02
Table 70. CANSTCH Register
CANSTCH (S:B2h) – CAN Message Object Status Register
Note:
No default value after reset.
DLCW
Bit Number
7
7
6
5
4
3
2
1
0
See Figure 39.
TXOK
6
Bit Mnemonic
DLCW
RXOK
BERR
SERR
CERR
AERR
TXOK
FERR
RXOK
5
Description
Data Length Code Warning
The incoming message does not have the DLC expected.
Whatever the frame type, the DLC field of the CANCONCH register
is updated by the received DLC.
Transmit OK
The communication enabled by transmission is completed.
When the controller is ready to send a frame, if two or more
message objects are enabled as producers, the lower index
message object (0 to 13) is supplied first. Must be cleared by
software.
This flag can generate an interrupt.
Receive OK
The communication enabled by reception is completed.
In the case of two or more message object reception hits, the lower
index message object (0 to 13) is updated first. Must be cleared by
software.
This flag can generate an interrupt.
bit Error (only in transmission)
The bit value monitored is different from the bit value sent.
Exceptions:
the monitored recessive bit sent as a dominant bit during the
arbitration field and the acknowledge slot detecting a dominant bit
during the sending of an error frame. Must be cleared by software.
This flag can generate an interrupt.
Stuff Error
Detection of more than five consecutive bits with the same polarity.
Must be cleared by software.
This flag can generate an interrupt.
CRC Error
The receiver performs a CRC check on each destuffed received
message from the start of frame up to the data field.
If this checking does not match with the destuffed CRC field, a
CRC error is set. Must be cleared by software.
This flag can generate an interrupt.
Form Error
The form error results from one or more violations of the fixed form
in the following bit fields:
CRC delimiter
acknowledgment delimiter
end_of_frame
Must be cleared by software.
This flag can generate an interrupt.
Acknowledgment Error
No detection of the dominant bit in the acknowledge slot. Must be
cleared by software.
This flag can generate an interrupt.
BERR
4
SERR
3
CERR
2
FERR
1
4126L–CAN–01/08
AERR
0