PIC16F76-I/SS Microchip Technology, PIC16F76-I/SS Datasheet - Page 317
PIC16F76-I/SS
Manufacturer Part Number
PIC16F76-I/SS
Description
IC MCU FLASH 8KX14 A/D 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F76-I/SS
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 8-bit
Controller Family/series
PIC16F
No. Of I/o's
22
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F76-I/SS
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC16F76-I/SS
Manufacturer:
MICROCHIP
Quantity:
7
Part Number:
PIC16F76-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 317 of 688
- Download datasheet (3Mb)
17.4.12
17.4.12.1 BF Status Flag
17.4.12.2 SSPOV Status Flag
17.4.12.3 WCOL Status Flag
1997 Microchip Technology Inc.
I
2
C Master Mode Reception
Master mode reception is enabled by programming the receive enable bit, RCEN
(SSPCON2<3>).
The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes
(high to low/low to high), and data is shifted into the SSPSR. After the falling edge of the eighth
clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into
the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set, and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is now in IDLE state, awaiting the next com-
mand. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can
then send an acknowledge bit at the end of reception, by setting the acknowledge sequence
enable bit, ACKEN (SSPCON2<4>).
In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from
SSPSR. It is cleared when the SSPBUF register is read.
In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR, and the BF
flag bit is already set from a previous reception.
If the user writes the SSPBUF when a receive is already in progress (i.e. SSPSR is still shifting
in a data byte), then the WCOL bit is set and the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
The SSP Module must be in an IDLE STATE before the RCEN bit is set, or the
RCEN bit will be disregarded.
Preliminary
Section 17. MSSP
DS31017A-page 17-41
17
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