PIC18LF2550-I/SP Microchip Technology, PIC18LF2550-I/SP Datasheet - Page 44
PIC18LF2550-I/SP
Manufacturer Part Number
PIC18LF2550-I/SP
Description
IC PIC MCU FLASH 16KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18F4550-IP.pdf
(430 pages)
8.PIC18LF2455-ISO.pdf
(430 pages)
Specifications of PIC18LF2550-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI/I2C/EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- PIC18F4550-IP PDF datasheet #7
- PIC18LF2455-ISO PDF datasheet #8
- Current page: 44 of 430
- Download datasheet (8Mb)
PIC18F2455/2550/4455/4550
3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• the primary clock source is not any of the XT or
TABLE 3-2:
DS39632C-page 42
Note 1:
is not stopped; and
HS modes.
Primary Device Clock
T1OSC or INTRC
2:
3:
4:
5:
(PRI_IDLE mode)
Before Wake-up
(Sleep mode)
INTOSC
In this instance, refers specifically to the 31 kHz INTRC clock source.
T
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
T
(parameter F12, Table 28-9); it is also designated as T
Execution continues during T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
CSD
OST
None
(parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs
is the Oscillator Start-up Timer period (parameter 32, Table 28-12). t
Microcontroller Clock Source
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(3)
(1)
IOBST
After Wake-up
XTPLL, HSPLL
XTPLL, HSPLL
XTPLL, HSPLL
XTPLL, HSPLL
INTOSC
INTOSC
INTOSC
INTOSC
XT, HS
XT, HS
XT, HS
XT, HS
(parameter 39, Table 28-12), the INTOSC stabilization period.
EC
EC
EC
EC
Preliminary
(3)
(3)
(3)
(3)
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
T
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
CSD
PLL
.
following the wake event is still required when
T
T
T
Exit Delay
OST
OST
OST
T
T
T
T
T
T
T
T
IOBST (5)
IOBST
None
None
CSD
CSD
CSD (2)
OST (4)
OST (4)
OST (4)
+ t
+ t
+ t
(2)
(2)
rc
rc
rc
(5)
(4)
(4)
(4)
rc
is the PLL lock time-out
© 2006 Microchip Technology Inc.
Clock Ready Status
Bit (OSCCON)
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS
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