DSPIC30F4011-20I/P Microchip Technology, DSPIC30F4011-20I/P Datasheet - Page 29
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DSPIC30F4011-20I/P
Manufacturer Part Number
DSPIC30F4011-20I/P
Description
IC DSPIC MCU/DSP 48K 40DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F4012-30ISO.pdf
(238 pages)
3.DSPIC30F4012-30ISO.pdf
(18 pages)
4.DSPIC30F4012-30ISO.pdf
(6 pages)
5.DSPIC30F4012-30ISO.pdf
(16 pages)
6.DSPIC30F4012-30ISO.pdf
(22 pages)
Specifications of DSPIC30F4011-20I/P
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
48KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F4011-20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4011-20I/P
Manufacturer:
MICROCHI
Quantity:
20 000
Company:
Part Number:
DSPIC30F4011-20I/PT
Manufacturer:
MSC
Quantity:
32
Company:
Part Number:
DSPIC30F4011-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
FIGURE 3-5:
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
© 2010 Microchip Technology Inc.
Data
Space
EA
Note: PSVPAG is an 8-bit register containing bits <22:15> of the program space address
BSET
MOV
MOV
MOV
Upper Half of Data
Space is Mapped
into Program Space
Data Address Space
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
16
DATA SPACE MEMORY MAP
CORCON,#2
#0x00, W0
W0, PSVPAG
0x9200, W0
EA<15> = 0
EA<15> = 1
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
15
15
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Space
0x8000
15
0xFFFF
0x0000
Concatenation
Address
PSVPAG
0x00
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
64-Kbyte data address space (including all Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 64-Kbyte data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y address
space from data space and address it using EAs
sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
A data space memory map is shown in
Figure 3-7
and Y data spaces are accessed for MCU and DSP
instructions.
8
dsPIC30F4011/4012
(1)
23
23
illustrates a graphical summary of how X
Program Space
15
Data Read
DS70135G-page 29
0
Figure
0x007FFE
0x000100
0x001200
3-6.