AT89C51CC02UA-RATUM Atmel, AT89C51CC02UA-RATUM Datasheet - Page 101

• Manufacturer Part Number: AT89C51CC02UA-RATUM
• Description: IC 8051 MCU 16K FLASH 32-VQFP
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC02UA-RATUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: CANADAPT28
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4126L–CAN–01/08
Table 66. CANBT2 Register
CANBT2 (S:B5h) – CAN bit Timing Registers 2
Note:
No default value after reset.
Bit Number
7
-
6 - 5
3 - 1
7
4
0
1. The CAN controller bit timing registers must be accessed only if the CAN controller is
disabled with the ENA bit of the CANGCON register set to 0.
See Figure 41.
SJW 1
6
Bit Mnemonic
SJW1:0
PRS2:0
-
-
-
SJW 0
5
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Re-synchronization Jump Width
To compensate for phase shifts between clock oscillators of
different bus controllers, the controller must re-synchronize on any
relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of
clock cycles. A bit period may be shortened or lengthened by a re-
synchronization.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Programming Time Segment
This part of the bit time is used to compensate for the physical
delay times within the network. It is twice the sum of the signal
propagation time on the bus line, the input comparator delay and
the output driver delay.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
PRS 2
Tsjw = Tscl x (SJW [1..0] +1)
Tprs = Tscl x (PRS[2..0] + 1)
3
AT/T89C51CC02
PRS 1
2
PRS 0
1
0
-
101