AT89C51CC02UA-RATUM Atmel, AT89C51CC02UA-RATUM Datasheet - Page 133

• Manufacturer Part Number: AT89C51CC02UA-RATUM
• Description: IC 8051 MCU 16K FLASH 32-VQFP
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC02UA-RATUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 20
• Number Of Timers: 1
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: CANADAPT28
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4126L–CAN–01/08
CAN (Txok, Rxok, Err or OvrBuf)
CAN Timer Overflow (OVRTIM)
External interrupt (INT0)
External interrupt (INT1)
PCA (CF or CCFn)
Interrupt Name
UART (RI or TI)
Timer 1 (TF1)
Timer 2 (TF2)
Timer0 (TF0)
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register. This register also contains a global disable bit
which must be cleared to disable all the interrupts at the same time.
Each interrupt source can also be individually programmed to one of four priority levels
by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the
bit values and priority levels associated with each combination.
Table 108. Priority Level bit Values
A low-priority interrupt can be interrupted by a high priority interrupt but not by another
low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of the higher priority level is serviced. If interrupt requests of the same priority
level are received simultaneously, an internal polling sequence determines which
request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence, See Table 109.
Table 109. Interrupt Priority Within Level
ADC (ADCI)
IPH.x
0
0
1
1
Interrupt Address Vector
000Bh
001Bh
002Bh
003Bh
004Bh
0003h
0013h
0033h
0023h
0043h
IPL.x
0
1
0
1
Interrupt Number
AT/T89C51CC02
10
2
4
7
6
8
1
3
5
9
Interrupt Level Priority
3 (Highest)
0 (Lowest)
Polling Priority
1
2
10
1
2
3
4
5
6
7
8
9
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