AT89C51CC02UA-RATUM Atmel, AT89C51CC02UA-RATUM Datasheet - Page 22

IC 8051 MCU 16K FLASH 32-VQFP

AT89C51CC02UA-RATUM

Manufacturer Part Number
AT89C51CC02UA-RATUM
Description
IC 8051 MCU 16K FLASH 32-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet

Specifications of AT89C51CC02UA-RATUM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
20
Number Of Timers
1
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
CANADAPT28
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Price
Part Number:
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Atmel
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Reset Recommendation
to Prevent Flash
Corruption
Idle Mode
Entering Idle Mode
Exiting Idle Mode
Power-down Mode
Entering Power-down Mode
22
AT/T89C51CC02
When a Flash program memory is embedded on-chip, it is strongly recommended to
use an external reset chip (brown out device) to apply a reset (Figure 7). It prevents sys-
tem malfunction during periods of insufficient power-supply voltage (power-supply
failure, power supply switched off, etc.).
Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The
status of the Port pins during Idle mode is detailed in Table 15.
To enter Idle mode, set the IDL bit in PCON register (See Table 16). The
A/T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The
instruction that sets IDL bit is the last instruction executed.
Note:
There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
2. Generate a reset.
Notes:
The Power-down mode places the A/T89C51CC02 in a very low power state. Power-
down mode stops the oscillator, freezes all clock at known states. The CPU status prior
to entering Power-down mode is preserved, i.e., the program counter, program status
word register retain their data for the duration of Power-down mode. In addition, the
SFRs and RAM contents are preserved. The status of the Port pins during Power-down
mode is detailed in Table 15.
To enter Power-down mode, set PD bit in PCON register. The A/T89C51CC02 enters
the Power-down mode upon execution of the instruction that sets PD bit. The instruction
that sets PD bit is the last instruction executed.
Hardware clears IDL bit in PCON register which restores the clock to the CPU. Exe-
cution resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes with the instruction immediately follow-
ing the instruction that activated Idle mode. The general purpose flags (GF1 and
GF0 in PCON register) may be used to indicate whether an interrupt occurred dur-
ing normal operation or during Idle mode. When Idle mode is exited by an interrupt,
the interrupt service routine may examine GF1 and GF0.
A logic high on the RST pin clears IDL bit in PCON register directly and asynchro-
nously. This restores the clock to the CPU. Program execution momentarily
resumes with the instruction immediately following the instruction that activated the
Idle mode and may continue for a number of clock cycles before the internal reset
algorithm takes control. Reset initializes the A/T89C51CC02 and vectors the CPU to
address C:0000h.
If IDL bit and PD bit are set simultaneously, the A/T89C51CC02 enters Power-down
mode. Then it does not go in Idle mode when exiting Power-down mode.
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle.
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated Idle
mode should not write to a Port pin or to the external RAM.
4126L–CAN–01/08

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