PIC18LF452-I/L Microchip Technology, PIC18LF452-I/L Datasheet - Page 213
![IC MCU FLASH 16KX16 A/D 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC18LF452-I/L
Manufacturer Part Number
PIC18LF452-I/L
Description
IC MCU FLASH 16KX16 A/D 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18LF452-I/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC18
No. Of I/o's
34
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
MSSP, SPI, I2C, PSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
1 x 16 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Package
44PLCC
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF452-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 213 of 332
- Download datasheet (6Mb)
20.0
The PIC18FXXX instruction set adds many enhance-
ments to the previous PICmicro instruction sets, while
maintaining an easy migration from these PICmicro
instruction sets.
Most instructions are a single program memory word
(16-bits), but there are three instructions that require
two program memory locations.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
The PIC18FXXX instruction set summary in Table 20-2
lists byte-oriented, bit-oriented, literal and control
operations. Table 20-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register designator 'f' specifies which file
register is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The bit field designator 'b' selects the number of the bit
affected by the operation, while the file register desig-
nator 'f' represents the number of the file in which the
bit is located.
© 2006 Microchip Technology Inc.
The file register (specified by ‘f’)
The destination of the result
(specified by ‘d’)
The accessed memory
(specified by ‘a’)
The file register (specified by ‘f’)
The bit in the file register
(specified by ‘b’)
The accessed memory
(specified by ‘a’)
INSTRUCTION SET SUMMARY
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
• The desired FSR register to load the literal value
• No operand required
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the Call or Return instructions
• The mode of the Table Read and Table Write
• No operand required
All instructions are a single word, except for three dou-
ble-word instructions. These three instructions were
made double-word instructions so that all the required
information is available in these 32 bits. In the second
word, the 4-MSbs are 1’s. If this second word is exe-
cuted as an instruction (by itself), it will execute as a
NOP.
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2
Two-word branch instructions (if true) would take 3 s.
Figure 20-1 shows the general formats that the
instructions can have.
All examples use the format ‘nnh’ to represent a
hexadecimal
hexadecimal digit.
The Instruction Set Summary, shown in Table 20-2,
lists the instructions recognized by the Microchip
Assembler (MPASM
Section 20.1 provides a description of each instruction.
(specified by ‘k’)
into (specified by ‘f’)
(specified by ‘—’)
(specified by ‘s’)
instructions (specified by ‘m’)
(specified by ‘—’)
number,
TM
).
PIC18FXX2
where
DS39564C-page 211
‘h’
signifies
s.
a
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