ATMEGA406-1AAU Atmel, ATMEGA406-1AAU Datasheet - Page 176
ATMEGA406-1AAU
Manufacturer Part Number
ATMEGA406-1AAU
Description
IC AVR MCU 40K 1MHZ 48LQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA406-1AAU
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
I²C
Peripherals
POR, WDT
Number Of I /o
18
Program Memory Size
40KB (20K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 25 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-30°C ~ 85°C
Package / Case
48-LQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire
Maximum Clock Frequency
1 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 30 C
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
1MHz
Total Internal Ram Size
2KB
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5/9/12/15/18/24V
Operating Supply Voltage (max)
25V
Operating Supply Voltage (min)
4V
On-chip Adc
10-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-30C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Controller Family/series
AVR MEGA
No. Of I/o's
18
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
1MHz
Rohs Compliant
Yes
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA406-1AAU
Manufacturer:
AT
Quantity:
20 000
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26.7
26.7.1
26.7.2
176
On-chip Debug Related Register
ATmega406
OCDR – On-chip Debug Register
MCUCR – MCU Control Register
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
The MCU Control Register contains control bits for general MCU functions.
• Bit 7 - JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value.
Note that this bit must not be altered when using the On-chip Debug system.
Bit
0x31 (0x51)
Read/Write
Initial Value
Bit
0x35 (0x55)
Read/Write
Initial Value
R/W
R/W
JTD
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
On-Chip Debug Register
PUD
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
IVSEL
R/W
R/W
1
0
1
0
IVCE
R/W
R/W
0
0
0
0
2548E–AVR–07/06
MCUCR
OCDR
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