AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 172

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32015G–AVR32–09/09
Transfer hierarchy:
fers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for
non-memory peripherals.
Figure 18-2. DMACA Transfer Hierarchy for Non-Memory Peripheral
Figure 18-3. DMACA Transfer Hierarchy for Memory
Block: A block of DMACA data. The amount of data (block length) is determined by the flow
controller. For transfers between the DMACA and memory, a block is broken directly into a
sequence of System Bus bursts and single transfers. For transfers between the DMACA and a
non-memory peripheral, a block is broken into a sequence of DMACA transactions (single and
bursts). These are in turn broken into a sequence of System Bus transfers.
Transaction: A basic unit of a DMACA transfer as determined by either the hardware or soft-
ware handshaking interface. A transaction is only relevant for transfers between the DMACA
and a source or destination peripheral if the source or destination peripheral is a non-memory
device. There are two types of transactions: single and burst.
System Bus
Transaction
Transfer
Burst
Block
Burst
System Bus
Transfer
Burst
Block
System Bus
Transaction
Transfer
Burst
Figure 18-2 on page 172
Burst
Block
System Bus
DMAC Transfer
Figure 18-3 on page 172
Transfer
Burst
Block
DMAC Transfer
System Bus
Transfer
Transaction
Burst
Burst
System Bus
Transfer
Block
Burst
System Bus
illustrates the hierarchy between DMACA trans-
Transfer
Single
Block
shows the transfer hierarchy for memory.
System Bus
Transfer
Single
System Bus
Transaction
Transfer
Single
Single
Block Transfer
Level
System Bus
Transfer Level
DMA Transfer
Level
AT32AP7001
Block Transfer
Level
DMA Transaction
Level
System Bus
Transfer Level
DMA Transfer
Level
172