AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 393

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 25-3. Baud Rate Generator
25.7.1.1
25.7.1.2
Table 25-2.
32015G–AVR32–09/09
Source Clock
3 686 400
4 915 200
5 000 000
MHz
CLK_USART/DIV
CLK
Baud Rate in Asynchronous Mode
Baud Rate Calculation Example
Baud Rate Example (OVER = 0)
CLK_USART
Reserved
Expected Baud
USCLKS
If the external CLK clock is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be longer than a CLK_USART period. The frequency of the signal
provided on CLK must be at least 4.5 times lower than CLK_USART.
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (BRGR). The
resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is
the highest possible clock and that OVER is programmed at 1.
Table 25-2
clock frequencies. This table also shows the actual resulting baud rate and the error.
0
1
3
2
38 400
38 400
38 400
Rate
Bit/s
Baudrate
shows calculations of CD to obtain a baud rate at 38400 bauds for different source
16-bit Counter
=
Calculation Result
--------------------------------------------
(
CD
8 2 Over
SelectedClock
(
–
6.00
8.00
8.14
USCLKS= 3
)CD
0
SYNC
)
CD
>1
1
0
CD
6
8
8
0
1
OVER
Sampling
Divider
Actual Baud Rate
FIDI
38 400.00
38 400.00
39 062.50
Bit/s
0
1
SYNC
AT32AP7001
CLK
BaudRate
Sampling
Clock
Clock
0.00%
0.00%
1.70%
Error
393