AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 394

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Table 25-2.
25.7.1.3
32015G–AVR32–09/09
Source Clock
12 000 000
12 288 000
14 318 180
14 745 600
18 432 000
24 000 000
24 576 000
25 000 000
32 000 000
32 768 000
33 000 000
40 000 000
50 000 000
60 000 000
70 000 000
7 372 800
8 000 000
Fractional Baud Rate in Asynchronous Mode
Baud Rate Example (OVER = 0) (Continued)
Expected Baud
The baud rate is calculated with the following formula:
The baud rate error is calculated with the following formula. It is not recommended to work with
an error higher than 5%.
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock
divider. This feature is only available when using USART normal mode. The fractional Baud
Rate is calculated using the following formula:
Baudrate
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
Rate
Error
BaudRate
=
=
---------------------------------------------------------------- -
⎛
⎝
1
8 2 Over
–
Calculation Result
(
⎛
⎝
ExpectedBaudRate
-------------------------------------------------- -
=
SelectedClock
–
ActualBaudRate
(
113.93
CLKUSART
12.00
13.02
19.53
20.00
23.30
24.00
30.00
39.06
40.00
40.69
52.08
53.33
53.71
65.10
81.38
97.66
) CD
⎛
⎝
+
FP
------ -
8
) CD
⎞
⎠
⎞
⎠
⁄
⎞
⎠
×
114
CD
12
13
20
20
23
24
30
39
40
40
52
53
54
65
81
98
16
Actual Baud Rate
38 400.00
38 461.54
37 500.00
38 400.00
38 908.10
38 400.00
38 400.00
38 461.54
38 400.00
38 109.76
38 461.54
38 641.51
38 194.44
38 461.54
38 580.25
38 265.31
38 377.19
AT32AP7001
0.00%
0.16%
2.40%
0.00%
1.31%
0.00%
0.00%
0.16%
0.00%
0.76%
0.16%
0.63%
0.54%
0.16%
0.47%
0.35%
0.06%
Error
394