AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 450
AT32AP7001-ALUT
Manufacturer Part Number
AT32AP7001-ALUT
Description
IC MCU 32BIT AVR32 208-LQFP
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7001-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, POR, PWM, WDT
Number Of I /o
90
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, ISI, MCI, PS2, SPI, TWI, USB
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
90
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 1 Channel
Package
208PQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32AP7001-ALUT
Manufacturer:
EVERLIGHT
Quantity:
12 000
- Current page: 450 of 829
- Download datasheet (12Mb)
26.7.3.1
26.7.3.2
32015G–AVR32–09/09
AC97 Controller Setup
Transmit Operation
The following operations must be performed in order to bring the AC97 Controller into an operat-
ing state:
The application must perform the following steps in order to send data via a channel to the AC97
Codec:
Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically
set by the AC97 Controller which allows the application to start a new write action. The applica-
tion can also wait for an interrupt notice associated with TXRDY in order to send data. The
interrupt remains active until TXRDY flag is cleared..
1. Enable the AC97 Controller clock in the power manager.
2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register (MR).
3. Configure the input channel assignment by controlling the AC97 Controller Input Assign-
4. Configure the output channel assignment by controlling the AC97 Controller Input
5. Configure sample width for Channel A and Channel B by writing the SIZE bit field in
6. Configure data Endianness for Channel A and Channel B by writing CEM bit field in
7. Configure the PIO controller to drive the RESET signal of the external Codec. The
8. Enable Channel A and/or Channel B by writing CEN bit field in CAMR and CBMR
•Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status
•Write data to the AC97 Controller Channel x Transmit Holding Register (CxTHR).
Register (CxSR). x being one of the 2 channels.
ment Register (ICA).
Assignment Register (OCA).
AC97C Channel A Mode Register (CAMR) and AC97C Channel B Mode Register
(CBMR). The application can write 10, 16, 18,or 20-bit wide PCM samples through the
AC97 interface and they will be transferred into 20-bit wide slots.
CAMR and CBMR registers. Data on the AC-link are shifted MSB first. The application
can write little- or big-endian data to the AC97 Controller interface.
RESET signal must fulfill external AC97 Codec timing requirements.
registers.
AT32AP7001
450
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