AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 559

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

30.4
30.4.1
30.4.2
32015G–AVR32–09/09
Functional Description
Write Access
Read Access
A page in NAND Flash and SmartMedia memories contains an area for main data and an addi-
tional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page
size corresponds to the number of words in the main data plus the number of words in the extra
area used for redundancy.
The only configuration required for ECC is the NAND Flash or the SmartMedia page size
(528/1056/2112/4224). Page size is configured setting the PAGESIZE field in the ECC Mode
Register (MR).
ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND
Flash or the SmartMedia is detected. Read and write access must start at a page boundary.
ECC is computed as soon as the counter reaches the page size. Values in the ECC Parity Reg-
ister (PR) and ECC NParity Register (NPR) are then valid and locked until a new start condition
(read/write command followed by five access address cycles).
Once the flash memory page is written, the computed ECC code is available in the ECC Parity
Error (PR) and ECC_NParity Error (NPR) registers. The ECC code value must be written by the
software application at the end of the page, in the extra area used for redundancy.
After reading main data in the page area, the application can perform read access to the extra
area used for redundancy. Error detection is automatically performed by the ECC controller. The
application can check the ECC Status Register (SR) for any detected errors.
It is up to the application to correct any detected error. ECC computation can detect four differ-
ent circumstances:
ECC Status Register, ECC Parity Register and ECC NParity Register are cleared when a
read/write command is detected or a software register is enabled.
For single bit Error Correction and double bit Error Detection (SEC-DED) hsiao code is used. 32-
bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit
•No error: XOR between the ECC computation and the ECC code stored at the end of the
•Recoverable error: Only the RECERR flag in the ECC Status register (SR) is set. The
•ECC error: The ECCERR flag in the ECC Status Register is set. An error has been detected
•Non correctable error: The MULERR flag in the ECC Status Register is set. Several
NAND Flash or SmartMedia page is equal to 0. No error flags in the ECC Status Register
(SR).
corrupted word offset in the read page is defined by the WORDADDR field in the ECC Parity
Register (PR). The corrupted bit position in the concerned word is defined in the BITADDR
field in the ECC Parity Register (PR).
in the ECC code stored in the Flash memory. The position of the corrupted bit can be found
by the application performing an XOR between the Parity and the NParity contained in the
ECC code stored in the flash memory.
unrecoverable errors have been detected in the flash memory page.
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