AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 619

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 32-12. Data OUT Transfer for Endpoint with One Bank
32015G–AVR32–09/09
USB Bus
Packets
RX_BK_RDY
(UDPHS_EPTSTAx)
FIFO (DPR)
Content
Token OUT
Host Sends Data Payload
Written by UDPHS Device
Data OUT 1
Data OUT 1
For OUT transfer, the bank will be automatically cleared by hardware when the application has
read all the bytes in the bank (the bank is empty).
Note: When a zero-length-packet is received, RX_BK_RDY bit in EPTSTAx is cleared automat-
ically by AUTO_VALID, and the application knows of the end of buffer by the presence of the
END_TR_IT.
Note: If the host sends a zero-length packet, and the endpoint is free, then the device sends an
ACK. No data is written in the endpoint, the RX_BY_RDY interrupt is generated, and the
BYTE_COUNT field in EPTSTAx is null.
– END_BUFFIT: Generate an interrupt when BUFF_COUNT in the DMASTATUSx
– END_TR_EN: End of transfer enable, the USBA device can put an end to the current
– END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB
– CHANN_ENB: Run and stop at end of buffer.
register reaches 0.
DMA transfer, in case of a short packet.
packet has been transferred by the DMA, if the USB transfer ended with a short
packet. (Beneficial when the receive size is unknown.)
Host Sends the Next Data Payload
Microcontroller Read
ACK
Set by Hardware
Microcontroller Transfers Data
Data OUT 1
Token OUT
Interrupt Pending
Data OUT 2
NAK
Cleared by Firmware,
Data Payload Written in FIFO
Token OUT
Host Resends the Next Data Payload
Written by UDPHS Device
Data OUT 2
Data OUT 2
AT32AP7001
ACK
619